Abstract: A processor is includes cache memory; an arithmetic processing section that a load request loading an object data stored at a memory to the cache memory; a cache control part patent a process corresponding to the received load request; a memory management part which requests the object data corresponding to the request from the cache control part and header information containing information indicating whether or not the object data is a latest for the memory, and receives the header information responded by the memory; and a data management part that manages a write control of the data to the cache memory, and receives the object data responded by the memory based on the request. The requested data is transmitted from the memory to the data management part held by a CPU node without being intervened by the memory management part.

Abstract: A device includes: a request-storage unit including entries configured to store requests and stopping issuance of a stored request when a flag is set based on an input configuration notification, in which the request-storage unit outputs a warning notification when the request stored in any of the entries has not been processed for more than a predetermined amount of time; a derived request-storage unit including derived entries configured to store derived requests derived from processing of requests stored in the request-storage unit; an arbitrating unit configured to arbitrate requests stored in the request-storage unit and derived requests stored in the derived request-storage unit, and to output the configuration notification based on the warning notification output from the request-storage unit; and a request-processing unit configured to process requests or derived requests arbitrated by the arbitrating unit, and to request-storage of derived requests derived by processing requests into the derived-stor