Patents by Inventor Daisuke Kawase

Daisuke Kawase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260140464
    Abstract: A processing device includes a process portion and a processor. The process portion performs medium processing on a transfer medium, subsequent to or prior to ejection of ink forming an image to be transferred from the transfer medium to a transfer-receival medium. The processor causes the process portion to perform one of the medium processing of forming additional information on the transfer medium in a non-transfer mode, or the medium processing of implementing a restriction procedure on the additional information formed on the transfer medium, or the medium processing of implementing an image transfer procedure on the image formed on the transfer medium and not implementing an information transfer procedure on the additional information formed on the transfer medium.
    Type: Application
    Filed: November 10, 2025
    Publication date: May 21, 2026
    Inventors: Daisuke KAWASE, Akihiro KAWAKITA, Shuichi TAMAKI
  • Publication number: 20260031295
    Abstract: Provided is a semiconductor DC breaker which has redundancy so as to be able to interrupt a current even if a semiconductor switching element for cutting off a current when an abnormal current is detected has failed. This semiconductor DC breaker 1 having a semiconductor switching element 21 that interrupts a main current when an abnormal current is detected comprises: a fuse 25 connected to the semiconductor switching element 21 in series; an abnormal current detection unit 11 that detects an abnormal current; and a gate drive unit 12 that turns off the semiconductor switching element 21 when the abnormal current is detected by the abnormal current detection unit 11. The magnitude of the abnormal current at which the semiconductor switching element 21 is to be turned off is set to be smaller than magnitude of a fusing current of the fuse 25.
    Type: Application
    Filed: April 11, 2023
    Publication date: January 29, 2026
    Inventors: Daisuke KAWASE, Koji SASAKI, Daisuke MAEDA, Kunihiko TOMIYASU, Takayuki KUSHIMA, Tomoyasu FURUKAWA
  • Patent number: 12463100
    Abstract: Provided is a semiconductor module comprising a power semiconductor chip, a base, an insulating substrate bonded to the base, a semiconductor chip bonded to the insulating substrate, and a case adhered to the base by means of an adhesive. The semiconductor module has a low variability but a high assembly quality and reliability enabling a decrease in stress between the case and an adhered portion of the base. The base includes a plate-like first material, and a second material coating the first material and having a linear coefficient of expansion greater than that of the first material. The case covers at least part of a side surface of the base and is adhered to the base at least on an upper surface of the base by means of the adhesive, and a linear expansion coefficient of the case is larger than the linear expansion coefficient of the first material.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: November 4, 2025
    Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
    Inventors: Kisho Ashida, Daisuke Kawase, Koji Sasaki
  • Publication number: 20250303690
    Abstract: A platen includes a platen plate, a platen support base, and a press surface. The platen plate includes a placement surface facing upward. A print medium is placed on the placement surface. The platen support base is disposed lower than the platen plate and includes a support pillar supporting the platen plate from below. The press surface is provided higher than a lowermost surface of the platen support base. The press surface faces downward and is configured for a press head to come into contact with the press surface when the press head performs pressing operation in a set state in which the platen is set on the press head.
    Type: Application
    Filed: March 12, 2025
    Publication date: October 2, 2025
    Inventors: Takuro YAMAZAKI, Daisuke KAWASE, Shuichi TAMAKI, Tetsuro KOBAYASHI
  • Publication number: 20250167908
    Abstract: An optical communication system includes: a master station device and a slave station device. The master station device generates a digital signal including one frame in which plural pieces of control information are stored, and transmits an optical signal including the generated digital signal and an analog main signal, to the slave station device via an optical fiber. The slave station device acquires at least one piece of control information out of the plural pieces of control information, from the digital signal included in the optical signal received from the master station device via the optical fiber.
    Type: Application
    Filed: February 21, 2023
    Publication date: May 22, 2025
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yusuke MIYAZEKI, Tomoyuki FUNADA, Keisuke JINEN, Isao KATSURA, Daisuke KAWASE, Naruto TANAKA
  • Publication number: 20250167885
    Abstract: An optical communication system includes a master station device, and a slave station device. The master station device generates a first digital signal including control information, and transmits, to the slave station device, a downlink optical signal including the generated first digital signal and an analog main signal. The slave station device acquires the first digital signal included in the downlink optical signal received from the master station device, and performs a loop-back process of transmitting an uplink optical signal including the acquired first digital signal to the master station device. The master station device acquires the control information from the first digital signal included in the uplink optical signal received from the slave station device.
    Type: Application
    Filed: February 21, 2023
    Publication date: May 22, 2025
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yusuke MIYAZEKI, Tomoyuki FUNADA, Keisuke JINEN, Isao KATSURA, Daisuke KAWASE, Naruto TANAKA
  • Publication number: 20250112631
    Abstract: To provide a technique enabling stable protection of a switching element at the time of short circuit by suppressing jumping of the voltage Vge between a gate terminal and a reference potential terminal at the time of occurrence of short circuit. A power semiconductor module having at least an upper arm, includes: a Zener diode connected between a gate terminal and a reference potential terminal and provided on the outside of a semiconductor chip of a switching element and provided on an insulating substrate; a casing which houses the insulating substrate; and a plurality of external electrodes provided to the casing and connected to the gate terminal and the reference potential terminal.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 3, 2025
    Inventors: Taiga ARAI, Katsuaki SAITO, Daisuke KAWASE, Akira MIMA, Takashi WADA
  • Publication number: 20250108632
    Abstract: A drying device includes a housing, a heater, a fan, and a processor. The housing includes an internal space housing a platen and an opening connected to the internal space and being of a size through which the platen passes. A medium to which an ink or a treatment liquid is applied is placed on the platen. The fan supplies heated air to the internal space. In a housed state of the platen housed in the internal space, the processor switches an air supply state of the heated air supplied by the fan from a first air supply state to a second air supply state different from the first air supply state by controlling at least one of the heater or the fan.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 3, 2025
    Inventors: Takuro YAMAZAKI, Daisuke KAWASE, Shuichi TAMAKI, Tetsuro KOBAYASHI
  • Publication number: 20250108633
    Abstract: A conveyance control device includes a conveyor, a first heater and a second heater, and a processor. The conveyor conveys a platen on which a print medium is placed. The first heater and the second heater are connected to a printer. The printer performs printing on the print medium on the platen. The first heater and the second heater execute a medium heating operation to heat the print medium on the platen. The processor controls the conveyor and conveys a target platen to one of the first heater or the second heater. The target platen is the platen on which the print medium is placed and is a control target.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 3, 2025
    Inventors: Daisuke KAWASE, Shuichi TAMAKI, Takuro YAMAZAKI, Tetsuro KOBAYASHI
  • Publication number: 20240355888
    Abstract: The present invention provides: a semiconductor device which has higher resistance to bias at high temperatures and high humidities than ever before, while achieving good connection between a field limiting layer and a field plate; and a power conversion device which uses this semiconductor device. A semiconductor device according to the present invention is characterized by comprising a floating field limiting layer that is provided in a termination region and a field plate that is electrically connected to the field limiting layer, and is also characterized in that: the field plate is formed of a polysilicon; the field plate and the field limiting layer are connected to each other via an Al electrode; and the connection between the field limiting layer and the Al electrode and the connection between the field plate and the Al electrode are established at different contacts.
    Type: Application
    Filed: November 11, 2022
    Publication date: October 24, 2024
    Inventors: Masaki SHIRAISHI, Daisuke KAWASE, Tetsuo ODA, Tomoyasu FURUKAWA, Yutaka KATO, Tsubasa MORITSUKA
  • Publication number: 20240297592
    Abstract: Provided is a power semiconductor module comprising: a gate terminal to which a control signal is inputted; a reference potential terminal disposed adjacent to the gate terminal with a predetermined interval from the gate terminal; a main circuit wiring disposed in the vicinity of the reference potential terminal and the gate terminal; and an electromagnetic shield disposed between the gate terminal and the reference potential terminal to shield induction field generated by current flowing through the main circuit wiring. The present invention is also characterized in that: the electromagnetic shield is integrally formed with the gate terminal and/or the reference potential terminal; and, in a portion between the gate terminal and the reference potential terminal, a gap that is not shielded by the electromagnetic shield as seen from a direction in which a magnetic flux of the induction field intersects with the electromagnetic shield, is 1 mm or less.
    Type: Application
    Filed: May 10, 2022
    Publication date: September 5, 2024
    Applicant: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
    Inventors: Taiga Arai, Daisuke Kawase, Akira Mima, Katsuaki Saito
  • Publication number: 20240145331
    Abstract: The power semiconductor module includes a base plate, a semiconductor chip mounted on a first main surface of the base plate, and a heat sink connected to a second main surface of the base plate, wherein: a chamfered part is provided at an end portion of at least one side of the second main surface; and, when the cross section of the base plate is viewed in a state in which the base plate is fixed to the heat sink, the slope of the second main surface of the base plate is discontinuous at the boundary between the chamfered part and an area of the second main surface other than the chambered part, and the angle between the bottom surface of the chamfered part of the base plate and the surface on the side of the heat sink where the base plate is fixed is 5° to 30°.
    Type: Application
    Filed: May 9, 2022
    Publication date: May 2, 2024
    Inventors: Hitoshi NISHIMORI, Keisuke HORIUCHI, Norio NAKAZATO, Daisuke KAWASE, Koji SASAKI
  • Patent number: 11942512
    Abstract: A termination structure in which a semiconductor active region is surrounded with a guard ring and capable of preventing corrosion of a metal layer connected to the guard ring includes: an active region and a guard ring region surrounding the active region. A guard ring is formed on the semiconductor substrate, and an interlayer insulating film is formed on the semiconductor substrate so as to cover the guard ring. A field plate is disposed on the interlayer insulating film and is electrically connected to the guard ring via a contact penetrating the interlayer insulating film. A protective film covers the field plate, which has a laminated structure including a first metal in contact with the guard ring and a second metal which is disposed in contact with the first metal and has a lower standard potential than the first metal.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 26, 2024
    Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
    Inventors: Tomoyasu Furukawa, Daisuke Kawase
  • Publication number: 20240006256
    Abstract: Provided is a semiconductor module comprising a power semiconductor chip, a base, an insulating substrate bonded to the base, a semiconductor chip bonded to the insulating substrate, and a case adhered to the base by means of an adhesive. The semiconductor module has a low variability but a high assembly quality and reliability enabling a decrease in stress between the case and an adhered portion of the base. The base includes a plate-like first material, and a second material coating the first material and having a linear coefficient of expansion greater than that of the first material. The case covers at least part of a side surface of the base and is adhered to the base at least on an upper surface of the base by means of the adhesive, and a linear expansion coefficient of the case is larger than the linear expansion coefficient of the first material.
    Type: Application
    Filed: October 15, 2021
    Publication date: January 4, 2024
    Applicant: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Kisho Ashida, Daisuke Kawase, Koji Sasaki
  • Publication number: 20210367028
    Abstract: A termination structure in which a semiconductor active region is surrounded with a guard ring and capable of preventing corrosion of a metal layer connected to the guard ring includes: an active region and a guard ring region surrounding the active region. A guard ring is formed on the semiconductor substrate, and an interlayer insulating film is formed on the semiconductor substrate so as to cover the guard ring. A field plate is disposed on the interlayer insulating film and is electrically connected to the guard ring via a contact penetrating the interlayer insulating film. A protective film covers the field plate, which has a laminated structure including a first metal in contact with the guard ring and a second metal which is disposed in contact with the first metal and has a lower standard potential than the first metal.
    Type: Application
    Filed: April 27, 2021
    Publication date: November 25, 2021
    Inventors: Tomoyasu FURUKAWA, Daisuke KAWASE
  • Patent number: 11070295
    Abstract: A PON system according to one manner of the present invention includes an optical line terminal (OLT), at least one optical network unit (ONU), and an optical fiber that connects the optical line terminal and the optical network unit to each other. A reception level category for categorizing a reception level in the optical network unit, of an optical signal sent from the optical line terminal through the optical fiber is set. In discovery processing for searching for and registering an unregistered optical network unit, the optical line terminal registers an optical network unit corresponding to the reception level category.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: July 20, 2021
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomoyuki Funada, Daisuke Umeda, Keisuke Jinen, Naruto Tanaka, Daisuke Kawase
  • Patent number: 10919149
    Abstract: A robot has a vertical 6-axis articulated arm having an offset arm having a fifth axis and length link, and mutually linking fourth and sixth axes. The fourth and sixth axes shaft centers are parallel. The articulated arm has a head portion designated as a control point. A position and an orientation targeted to the control point is processed by an inverse transform to calculate angles of the axes. A provisional target position of the sixth axis is obtained by subtracting the link length from a target position of the sixth axis. The link length to the provisional target position is given zero to perform the inverse transform process. Processed results are evaluated. Until a difference between a calculated sixth-axis angles and provisionally decided sixth-axis angles becomes equal to or less than a predetermined value, processes started from the angle provisional decision of the sixth axis are repeatedly performed.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: February 16, 2021
    Assignee: DENSO WAVE INCORPORATED
    Inventors: Daisuke Kawase, Yuto Kawachi, Masanori Sato
  • Patent number: 10899013
    Abstract: In an eccentricity error correction method for an angle detector, an output shaft angle is determined in at least three measurement positions. A difference between an arm angle value at each measurement position and the output shaft angle detected at each measurement position is determined as an eccentricity error. An error curve indicates a relationship between the arm angle value and the eccentricity error, and is determined as a function of the arm angle value by approximating the eccentricity error at each measurement position with a sine wave of which a single cycle is a single rotation of the arm. A correction formula that associates the output shaft angle and the arm angle value is determined using the error curve. A correction value corresponds to the detected output shaft angle, and is determined based on the correction formula and correcting the eccentricity error when the arm is rotated.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: January 26, 2021
    Assignee: DENSO WAVE INCORPORATED
    Inventors: Daisuke Kawase, Yuto Kawachi, Hiroaki Shiratori, Takafumi Fukuoka
  • Patent number: 10885330
    Abstract: An image processing apparatus capable of easily generating a two-dimensional panoramic image at a high speed from a plurality of three-dimensional images includes an acquisition unit configured to acquire a generation condition of a first en-face image generated from a first three-dimensional image of an target eye, a first generation unit configured to generate a second en-face image from a second three-dimensional image of the target eye by applying the generation condition acquired by the acquisition unit to the second three-dimensional image, and a second generation unit configured to generate a combined image by combining the first en-face image with the second en-face image.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 5, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Daisuke Kawase, Hiroki Uchida, Osamu Sagano
  • Patent number: 10847614
    Abstract: A semiconductor device including: a semiconductor element; and a first electrode formed on a first surface of the semiconductor element. The first electrode has a stacked structure including a first electroless Ni plating layer. The first electroless Ni plating layer contains nickel (Ni) and phosphorus (P) as a composition. A phosphorus (P) concentration of the first electroless Ni plating layer is 2.5 wt % to 6 wt % inclusive, and a crystallization rate of Ni3P in the first electroless Ni plating layer is 0% to 20% inclusive.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 24, 2020
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Tomoyasu Furukawa, Toshiaki Morita, Daisuke Kawase, Toshihito Tabata