Patents by Inventor Daisuke Kishimoto

Daisuke Kishimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7821014
    Abstract: A semiconductor device and a manufacturing method thereof uses a semiconductor substrate of silicon carbide. On one principal surface side of the substrate, at its central section, a layer of silicon carbide or gallium nitride as a semiconductor layer having the thickness at least necessary for breakdown voltage blocking is epitaxially grown or formed from part of the substrate. A recess is formed in the other principal surface side of substrate at a position facing the central section. A supporting section surrounds the bottom of the recess and provides the side face of the recess. The recess is formed by processing such as dry etching. The semiconductor device, even though the semiconductor substrate is made thinner for the realization of small on-resistance, can maintain the strength of the semiconductor substrate capable of reducing occurrence of a wafer cracking during the manufacturing process.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: October 26, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Yoshiyuki Yonezawa, Daisuke Kishimoto
  • Patent number: 7510975
    Abstract: In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 ?m or narrower in width and even when the trenches are 1 ?m or narrower in width.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: March 31, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Daisuke Kishimoto, Hitoshi Kuribayashi, Yuji Sano, Akihiko Ohi, Yoshihiko Nagayasu
  • Patent number: 7355257
    Abstract: A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: April 8, 2008
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno
  • Publication number: 20070210316
    Abstract: A semiconductor device and a manufacturing method thereof uses a semiconductor substrate of silicon carbide. On one principal surface side of the substrate, at its central section, a layer of silicon carbide or gallium nitride as a semiconductor layer having the thickness at least necessary for breakdown voltage blocking is epitaxially grown or formed from part of the substrate. A recess is formed in the other principal surface side of substrate at a position facing the central section. A supporting section surrounds the bottom of the recess and provides the side face of the recess. The recess is formed by processing such as dry etching. The semiconductor device, even though the semiconductor substrate is made thinner for the realization of small on-resistance, can maintain the strength of the semiconductor substrate capable of reducing occurrence of a wafer cracking during the manufacturing process.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 13, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Yoshiyuki YONEZAWA, Daisuke KISHIMOTO
  • Publication number: 20070015333
    Abstract: A method of manufacturing a semiconductor device is disclosed that includes the treating the surface of a SiC semiconductor substrate prior to forming a gate oxide film on the SiC semiconductor substrate in order to etch the SiC semiconductor substrate by several nm to 0.1 ?m with hydrogen in a reaction furnace. The treating is conducted a reduced pressure in the furnace, at a temperature of 1500° C. or higher. The manufacturing method facilitates the removal of particles and oxide residues remaining on the trench inner wall after trench etching in the manufacturing process for manufacturing a SiC semiconductor device having a fine trench-type MOS gate structure.
    Type: Application
    Filed: June 13, 2006
    Publication date: January 18, 2007
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Daisuke Kishimoto, Takeshi Tawara, Takashi Tsuji, Shunsuke Izumi
  • Publication number: 20060256487
    Abstract: A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region.
    Type: Application
    Filed: March 8, 2006
    Publication date: November 16, 2006
    Applicant: FUJI ELECTRIC HOLDING CO., LTD.
    Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno
  • Publication number: 20060252243
    Abstract: An epitaxial film deposition system includes a reactor, a susceptor, a wafer heating unit, a reactant gas supply orifice, and an aperture for venting the reactant gas. The reactant gas is supplied to a reactor region between the susceptor and a graphite plate so as to circulate in layered flow in a direction along the reactor inner wall in the planar direction of a mounted SiC wafer. The temperature of the wafer is controlled by a high frequency coil and halogen lamps based on temperatures detected by a pyrometer. By circulating the reactant gas over the surface of the stationary wafer, it is possible to form, under various process conditions, an SiC epitaxial film having good film quality and good uniformity of film thickness, without providing any wafer rotation mechanism.
    Type: Application
    Filed: April 6, 2006
    Publication date: November 9, 2006
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Daisuke Kishimoto, Takeshi Tawara, Shunsuke Izumi
  • Publication number: 20060154438
    Abstract: In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 ?m or narrower in width and even when the trenches are 1 ?m or narrower in width.
    Type: Application
    Filed: September 23, 2005
    Publication date: July 13, 2006
    Inventors: Daisuke Kishimoto, Hitoshi Kuribayashi, Yuji Sano, Akihiko Ohi, Yoshihiko Nagayasu
  • Patent number: 7029977
    Abstract: A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: April 18, 2006
    Assignees: Fuji Electric Holdings Co., Ltd., Shin-Etsu Handotai Co., Ltd.
    Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno, Ryohsuke Shimizu, Satoshi Oka
  • Publication number: 20040185665
    Abstract: A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 23, 2004
    Applicants: FUJI ELECTRIC HOLDINGS CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno, Ryosuke Shimizu, Satoshi Oka
  • Patent number: 5715358
    Abstract: In the event of recording a picture signal for left eye and a picture signal for right eye, a picture signal for one of right and left eyes limited in band by a low pass filter as being an additional signal and a picture signal for the other eye as being a primary signal, and the additional signal together with the primary signal are recorded on recording medium.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: February 3, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Ohnaka, Katsuhiko Matsushita, Daisuke Kishimoto, Minoru Takahashi, Minoru Kume, Mitsutaka Komoike, Katsunori Hirase, Tatsuo Tanaka, Hirotsugu Murashima, Osamu Idegata, Masafumi Nishi
  • Patent number: 4767516
    Abstract: A magnetic recording tape making process and apparatus is disclosed. The apparatus includes a first depositing station which utilizes a the sputtering process for depositing a seed layer on a substrate with an initial incident angle of about 5.degree., and a second depositing station for depositing, over the seed layer, an extended layer with an initial incident angle of about 45.degree.. The seed layer has a thickness of about 0.01 micrometer, and is defined by young crystalline columns of magnetic material densely and perpendicularly formed on the substrate. The extended layer is defined by extended crystalline columns over the young crystalline columns through self-epitaxial growth. The completed magnetic film defined by the two layers has a high residual magnetization ratio MV/MH and also a high perpendicular coercivity Hcv.
    Type: Grant
    Filed: May 19, 1986
    Date of Patent: August 30, 1988
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshio Nakatsuka, Minoru Kume, Daisuke Kishimoto