Patents by Inventor Daisuke Koike

Daisuke Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260082954
    Abstract: An isolator includes a substrate, a first chip, and a second chip. The substrate includes an insulation layer and a pair of coils. The pair of coils are opposite to each other in a thickness direction via the insulation layer. The first chip is disposed to face one surface of the substrate. The first chip is connected to one of the pair of coils. The second chip is disposed to face the other surface of the substrate. The second chip is connected to the other of the pair of coils.
    Type: Application
    Filed: February 21, 2025
    Publication date: March 19, 2026
    Inventors: Yuusuke IMAIZUMI, Daijo CHIDA, Hitoshi IMAI, Daisuke KOIKE, Shiro OKADA
  • Publication number: 20260060126
    Abstract: A semiconductor device according to an embodiment includes a semiconductor chip, a substrate, and an adhesive layer. The substrate supports the semiconductor chip. The adhesive layer is disposed between the semiconductor chip and the substrate. The adhesive layer bonds the semiconductor chip and the substrate. The adhesive layer has a first portion and a plurality of second portions. The first portion is formed of a first material. The plurality of second portions are formed of a second material. The second material has a greater elastic modulus and a greater thermal conductivity than the first material. The second portions are located inside the first portion. Each of the second portions is in contact with and connects the semiconductor chip and the substrate.
    Type: Application
    Filed: October 29, 2025
    Publication date: February 26, 2026
    Inventor: Daisuke Koike
  • Publication number: 20250357411
    Abstract: A first conductor includes a first portion, a second portion, and a third portion. The first portion is in contact with the first electrode and has a second length in the first direction that is shorter than the first length. The second portion is located farther in a second direction than the first portion, is connected to the first portion, and has a third length in the first direction that is longer than the second length. The third portion is located farther in the second direction than the second portion, is connected to the second portion, and is exposed from a sealing resin.
    Type: Application
    Filed: September 11, 2024
    Publication date: November 20, 2025
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Eitaro MIYAKE, Fumiyoshi KAWASHIRO, Toshihiro TSUJIMURA, Daisuke KOIKE
  • Patent number: 12421479
    Abstract: According to one embodiment, there is provided a cleaning agent. The cleaning agent includes an azole-based compound having a group including at least one selected from the group consisting of a glycidyl group, a hydrolyzable silyl group, and an amino group.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: September 23, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Daisuke Koike, Yuning Tsai
  • Publication number: 20250105125
    Abstract: An isolator according to one embodiment, includes a substrate and a plurality of leads. The substrate includes a lower surface, a plurality of coils, and a plurality of conductive parts. The lower surface has a quadrilateral shape. The plurality of coils includes a first coil, and a second coil. The plurality of conductive parts includes a first conductive part, a second conductive part, a third conductive part, and a fourth conductive part. The first conductive part includes a first terminal. The second conductive part includes a second terminal. The third conductive part includes a third terminal. The fourth conductive part includes a fourth terminal. The plurality of leads includes a first lead, a second lead, a third lead, and a fourth lead. The plurality of leads includes a metal.
    Type: Application
    Filed: April 16, 2024
    Publication date: March 27, 2025
    Inventor: Daisuke KOIKE
  • Publication number: 20240312860
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor chip; a conductive sheet provided on the semiconductor chip; and a metal plate provided on the conductive sheet. The metal plate has a step portion that is provided on a lateral surface, or a groove portion that is provided on a bottom surface.
    Type: Application
    Filed: September 14, 2023
    Publication date: September 19, 2024
    Inventors: Daisuke KOIKE, Hisashi TOMITA, Yuning TSAI, Yutaro HAYASHI
  • Patent number: 12087672
    Abstract: This semiconductor device includes: a bed including a first upper surface having a plurality of first grooves and a first lower surface; a first bonding material provided on the first upper surface and in contact with the first grooves; a semiconductor chip including a second upper surface having a first electrode and a second electrode, and a second lower surface, the semiconductor chip being provided on the first bonding material and having the second lower surface connected to the first bonding material; a second bonding material provided on the first electrode and connected to the first electrode; and a first connector having a first end having a plurality of second grooves and connected to the second bonding material, and a second end.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: September 10, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Daisuke Koike
  • Patent number: 11769714
    Abstract: Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: September 26, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Daisuke Koike
  • Patent number: 11769715
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: September 26, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Publication number: 20230095013
    Abstract: According to one embodiment, there is provided a cleaning agent. The cleaning agent includes an azole-based compound having a group including at least one selected from the group consisting of a glycidyl group, a hydrolyzable silyl group, and an amino group.
    Type: Application
    Filed: February 24, 2022
    Publication date: March 30, 2023
    Inventors: Daisuke Koike, Yuning Tsai
  • Publication number: 20230089603
    Abstract: This semiconductor device includes: a bed including a first upper surface having a plurality of first grooves and a first lower surface; a first bonding material provided on the first upper surface and in contact with the first grooves; a semiconductor chip including a second upper surface having a first electrode and a second electrode, and a second lower surface, the semiconductor chip being provided on the first bonding material and having the second lower surface connected to the first bonding material; a second bonding material provided on the first electrode and connected to the first electrode; and a first connector having a first end having a plurality of second grooves and connected to the second bonding material, and a second end.
    Type: Application
    Filed: March 7, 2022
    Publication date: March 23, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Daisuke Koike
  • Patent number: 11476223
    Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: October 18, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daisuke Koike, Fumiyoshi Kawashiro
  • Patent number: 11437339
    Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 6, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daisuke Koike, Fumiyoshi Kawashiro
  • Publication number: 20220246504
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Patent number: 11342249
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 24, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Publication number: 20220077027
    Abstract: Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second
    Type: Application
    Filed: July 5, 2021
    Publication date: March 10, 2022
    Inventor: Daisuke Koike
  • Publication number: 20210082719
    Abstract: A conductive fluid discharge head includes: a first nozzle provided at a center of the conductive fluid discharge head; a plurality of second nozzles provided outside the first nozzle; and a fluid holding container provided on fluid outlets side of the first nozzle and the second nozzle, the fluid holding container having a recessed shape. The second nozzle protrudes toward the fluid outlet side than the first nozzle by a length of equal to or greater than 50 ?m and equal to or smaller than 150 ?m.
    Type: Application
    Filed: January 29, 2020
    Publication date: March 18, 2021
    Inventor: Daisuke Koike
  • Publication number: 20210074611
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Application
    Filed: February 10, 2020
    Publication date: March 11, 2021
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Publication number: 20210066234
    Abstract: A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.
    Type: Application
    Filed: January 29, 2020
    Publication date: March 4, 2021
    Inventors: Daisuke Koike, Fumiyoshi Kawashiro
  • Publication number: 20100038031
    Abstract: Even in the case of a thin semiconductor chip, the semiconductor chip is delaminated from an adhesive sheet so as to prevent cracking. A pick-up apparatus 1 has a stage 100 on which a dicing sheet 13 is placed, a slider which comes into contact with a back surface of the dicing sheet 13 and moves horizontally, in plan view, with respect to a semiconductor chip 12, a slider housing portion which is formed in the stage 100 and houses the slider, and a suction mechanism 500 which is coupled to the stage 100 and suctions the slider housing portion. On the stage 100, the dicing sheet 13 is placed in a position where the semiconductor chip 12 is opposed to the slider housing portion. The slider is provided with a plurality of slits on a side where the slider comes into contact with the dicing sheet 13. The slit is in communication with the slider housing portion 102.
    Type: Application
    Filed: August 31, 2009
    Publication date: February 18, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Daisuke Koike