Patents by Inventor Daisuke Komada
Daisuke Komada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11944456Abstract: A ceramic guide device includes a columnar ceramic guide including a first portion including a first end, a second portion including a second end and having a smaller diameter than a diameter of the first portion, and a third portion disposed between the first portion and the second portion, the columnar ceramic guide provided with an insertion hole through which a long wire electrode can be inserted from the first end to the second end; and the long wire electrode that penetrates through the insertion hole, the long wire electrode including a first protruding portion projecting from the first end, and a second protruding portion projecting from the second end.Type: GrantFiled: January 31, 2019Date of Patent: April 2, 2024Assignees: KYOCERA Corporation, TOHOKU UNIVERSITYInventors: Daisuke Komada, Hajime Mushiake, Tomokazu Ohshiro
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Publication number: 20230181009Abstract: A tube assembly for a living organism includes a tube and a first ferrule. The tube is partially placeable into a living organism. The tube includes a first end, a second end, a through-hole, and a lens. The through-hole extends in a first direction from the second end to the first end. The first ferrule covers an outer periphery of the tube in the first direction. The lens is located in a portion of the through-hole including at least the first end. The tube and the first ferrule contain a ceramic material.Type: ApplicationFiled: May 14, 2021Publication date: June 15, 2023Applicants: KYOCERA Corporation, OSAKA UNIVERSITYInventors: Daisuke KOMADA, Makoto OSANAI
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Patent number: 11675141Abstract: An optical connector ferrule, an optical connector, and a composite fiber connecting assembly are provided. The optical connector ferrule includes a stationary ferrule having a first through-hole, a composite fiber, and a connecting ferrule having a second through-hole. The composite fiber includes a first optical fiber and a signal wire, and is placed in the first through-hole in the stationary ferrule. The connecting ferrule includes a conductive path. The stationary ferrule has a second end face abutting a third end face of the connecting ferrule. The first optical fiber has an end connected to an end of the second through-hole. The signal wire and the conductive path are connected to each other.Type: GrantFiled: August 30, 2019Date of Patent: June 13, 2023Assignees: KYOCERA Corporation, TOHOKU UNIVERSITYInventors: Daisuke Komada, Hiroki Tachibana, Ko Matsui, Yuanyuan Guo
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Publication number: 20210181434Abstract: An optical connector ferrule, an optical connector, and a composite fiber connecting assembly are provided. The optical connector ferrule includes a stationary ferrule having a first through-hole, a composite fiber, and a connecting ferrule having a second through-hole. The composite fiber includes a first optical fiber and a signal wire, and is placed in the first through-hole in the stationary ferrule. The connecting ferrule includes a conductive path. The stationary ferrule has a second end face abutting a third end face of the connecting ferrule. The first optical fiber has an end connected to an end of the second through-hole. The signal wire and the conductive path are connected to each other.Type: ApplicationFiled: August 30, 2019Publication date: June 17, 2021Applicants: KYOCERA Corporation, TOHOKU UNIVERSITYInventors: Daisuke KOMADA, Hiroki TACHIBANA, Ko MATSUI, Yuanyuan GUO
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Publication number: 20210045688Abstract: A ceramic guide device includes a columnar ceramic guide including a first portion including a first end, a second portion including a second end and having a smaller diameter than a diameter of the first portion, and a third portion disposed between the first portion and the second portion, the columnar ceramic guide provided with an insertion hole through which a long wire electrode can be inserted from the first end to the second end; and the long wire electrode that penetrates through the insertion hole, the long wire electrode including a first protruding portion projecting from the first end, and a second protruding portion projecting from the second end.Type: ApplicationFiled: January 31, 2019Publication date: February 18, 2021Applicants: KYOCERA Corporation, TOHOKU UNIVERSITYInventors: Daisuke KOMADA, Hajime MUSHIAKE, Tomokazu OHSHIRO
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Publication number: 20090093379Abstract: The present invention relates to a spot pin (2) including: a liquid holding portion (21) including a tubular portion and defining a liquid holding space (27) for holding a liquid; and an upper limit position definition portion positioned in a middle of the liquid holding portion (21) in an axial direction and defining the upper limit position of the liquid held in the liquid holding portion (21). The upper limit position definition portion has one or a plurality of outside air communication holes (24) communicated with the liquid holding space (27) and opened in the circumferential surface of the liquid holding portion (21).Type: ApplicationFiled: April 28, 2006Publication date: April 9, 2009Applicant: KYOCERA CORPORATIONInventor: Daisuke Komada
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Patent number: 7119009Abstract: A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer.Type: GrantFiled: July 27, 2004Date of Patent: October 10, 2006Assignee: Fujitsu LimitedInventors: Kenichi Watanabe, Daisuke Komada, Fumihiko Shimpuku
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Publication number: 20050001323Abstract: A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer.Type: ApplicationFiled: July 27, 2004Publication date: January 6, 2005Applicant: FUJITSU LIMITEDInventors: Kenichi Watanabe, Daisuke Komada, Fumihiko Shimpuku
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Patent number: 6787907Abstract: A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer.Type: GrantFiled: December 14, 2000Date of Patent: September 7, 2004Assignee: Fujitsu LimitedInventors: Kenichi Watanabe, Daisuke Komada, Fumihiko Shimpuku
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Patent number: 6787474Abstract: The surface of an insulating film made of silicon-containing insulating material is covered with a mask pattern. The insulating film is dry-etched by using the mask pattern as a mask and etching gas which contains C4F8 gas and CxFy gas (wherein x and y are an integer and satisfy x≧5 and y≦(2x−1). In the dry-etching process, a sufficient etching selection ratio can be obtained between a layer to be etched and an underlying etching stopper film.Type: GrantFiled: January 9, 2002Date of Patent: September 7, 2004Assignee: Fujitsu LimitedInventor: Daisuke Komada
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Patent number: 6769819Abstract: An optical device module is provided which includes an optical device, an optical fiber an end of which is optically coupled to the optical device, a package containing the optical device and the optical fiber, and an insertion tube fixed air-tightly through the wall of the package, the optical fiber extending through the insertion tube out of the package, wherein the end portion of the optical fiber is offset with respect to the fixed portion, by the insertion tube, of the optical fiber to bend the optical fiber between the end portion and the fixed portion of the optical fiber, then avoiding the displacement of the end of the fiber to be coupled to the optical device due to a change in environment temperatures of the module, and minimize the temperature dependence of device performance.Type: GrantFiled: March 28, 2001Date of Patent: August 3, 2004Assignee: Kyocera CorporationInventors: Tsuyoshi Tanaka, Daisuke Komada, Shiro Yonekura
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Patent number: 6627554Abstract: A semiconductor device manufacturing method having a multi-layered wiring structure comprises the steps of forming an insulating film over a semiconductor substrate, coating resist on the insulating film, forming a wiring pattern window in the resist, forming a wiring recess by etching the insulating film via the window, removing the resist, removing a reaction product existing on the insulating film by exposing the insulating film to a plasma atmosphere using an inactive gas, and burying a metal film into the wiring recess to form a wiring.Type: GrantFiled: March 27, 2000Date of Patent: September 30, 2003Assignee: Fujitsu LimitedInventor: Daisuke Komada
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Patent number: 6599841Abstract: A method for fabricating a semiconductor device including a conductive pattern having a first layer including Ti and a second layer including W is presented. The method includes the steps of patterning the conductive pattern by a dry etching and exposing the conductive pattern after the step of the patterning to a plasma containing O, thereby removing the remaining Cl which induces an aftercorrosion problem of the conductive pattern containing the Ti.Type: GrantFiled: June 29, 1999Date of Patent: July 29, 2003Assignee: Fujitsu LimitedInventor: Daisuke Komada
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Publication number: 20030068582Abstract: A first film is formed on a semiconductor substrate, the first film being made of material having a different etching resistance from silicon carbide. A second film of hydrogenated silicon carbide is formed on the first film. A resist film with an opening is formed on the second film. By using the resist mask as an etching mask, the second film is dry-etched by using mixture gas of fluorocarbon gas added with at least one of SF6 and NF3. The first film is etched by using the second film as a mask. A semiconductor device manufacture method is provided which utilizes a process capable of easily removing an etching stopper film or hard mask made of SiC.Type: ApplicationFiled: January 30, 2002Publication date: April 10, 2003Applicant: Fujitsu LimitedInventors: Daisuke Komada, Katsumi Kakamu
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Publication number: 20030064603Abstract: The surface of an insulating film made of silicon-containing insulating material is covered with a mask pattern. The insulating film is dry-etched by using the mask pattern as a mask and etching gas which contains C4F8 gas and CxFy gas (wherein x and y are an integer and satisfy x≧5 and y≦(2x−1). In the dry-etching process, a sufficient etching selection ratio can be obtained between a layer to be etched and an underlying etching stopper film.Type: ApplicationFiled: January 9, 2002Publication date: April 3, 2003Applicant: Fujitsu LimitedInventor: Daisuke Komada
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Patent number: 6498089Abstract: A semiconductor integrated circuit device, having: a plurality of semiconductor elements formed in a central circuit area of a semiconductor chip; a plurality of insulating layers formed on the semiconductor chip; cavities for forming wiring layers of a multi-layer structure, each of the cavities in each wiring layer having a via hole and a wiring pattern trench; wiring layers of the multi-layer structure including a via conductor filled in the via hole and a wiring pattern filled in the wiring pattern trench; moisture-proof ring trenches of a multi-layer structure corresponding to the cavities for forming the wiring layers of the multi-layer structure, the moisture-proof ring trenches surrounding the circuit area in a loop-shape and formed through the insulating layers, a width of each of the moisture-proof ring trenches corresponding to a corresponding one or ones of the via holes being set smaller than a minimum diameter of the via holes; and a conductive moisture-proof ring filled in a corresponding one oType: GrantFiled: September 19, 2001Date of Patent: December 24, 2002Assignee: Fujitsu LimitedInventor: Daisuke Komada
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Publication number: 20020125577Abstract: A semiconductor integrated circuit device, having: a plurality of semiconductor elements formed in a central circuit area of a semiconductor chip; a plurality of insulating layers formed on the semiconductor chip; cavities for forming wiring layers of a multi-layer structure, each of the cavities in each wiring layer having a via hole and a wiring pattern trench; wiring layers of the multi-layer structure including a via conductor filled in the via hole and a wiring pattern filled in the wiring pattern trench; moisture-proof ring trenches of a multi-layer structure corresponding to the cavities for forming the wiring layers of the multi-layer structure, the moisture-proof ring trenches surrounding the circuit area in a loop-shape and formed through the insulating layers, a width of each of the moisture-proof ring trenches corresponding to a corresponding one or ones of the via holes being set smaller than a minimum diameter of the via holes; and a conductive moisture-proof ring filled in a corresponding one oType: ApplicationFiled: September 19, 2001Publication date: September 12, 2002Applicant: Fujitsu LimitedInventor: Daisuke Komada
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Publication number: 20020008323Abstract: A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer.Type: ApplicationFiled: December 14, 2000Publication date: January 24, 2002Applicant: Fujitsu Limited, Kawasaki, JapanInventors: Kenichi Watanabe, Daisuke Komada, Fumihiko Shimpuku
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Publication number: 20010026664Abstract: An optical device module is provided which includes an optical device, an optical fiber an end of which is optically coupled to the optical device, a package containing the optical device and the optical fiber, and an insertion tube fixed air-tightly through the wall of the package, the optical fiber extending through the insertion tube out of the package, wherein the end portion of the optical fiber is offset with respect to the fixed portion, by the insertion tube, of the optical fiber to bend the optical fiber between the end portion and the fixed portion of the optical fiber, then avoiding the displacement of the end of the fiber to be coupled to the optical device due to a change in environment temperatures of the module, and minimize the temperature dependence of device performance.Type: ApplicationFiled: March 28, 2001Publication date: October 4, 2001Applicant: KYOCERA CORPORATIONInventors: Tsuyoshi Tanaka, Daisuke Komada, Shiro Yonekura
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Publication number: 20010003675Abstract: A method for fabricating a semiconductor device including a conductive pattern having a first layer including Ti and a second layer including W is presented. The method includes the steps of patterning the conductive pattern by a dry etching and exposing the conductive pattern after the step of the patterning to a plasma containing O, thereby removing the remaining Cl which induces an aftercorrosion problem of the conductive pattern containing the Ti.Type: ApplicationFiled: June 29, 1999Publication date: June 14, 2001Applicant: FUJITSU LIMITEDInventor: DAISUKE KOMADA