Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for indicating location status. A computing device can receive a query from a user device, a current time, and a location for the user device. The computing device identifies results responsive to the query, including one or more business results that are each associated with a business location and operating hours. The computing device can select a subset of the business results as open results based on the operating hours of the business results, the current time, and travel times from the device location to the respective business locations. Data can be provided for a search engine results page that designates the subset of the business results as open results.

Abstract: Electrical isolation in non-volatile memory is provided by air gaps formed using sacrificial films of differing etch rates. A high etch rate material is formed in an isolation trench. Flowable chemical vapor deposition processes are used to form high etch rate films, and curing is performed to increase their etch rate. A low etch material is formed over the high etch rate material and provides a controlled etch back between charge storage regions in a row direction. A discrete low etch rate layer can be formed or the high etch rate material can be oxidized to form an upper region with a lower etch rate. A controlled etch back enables formation of a wrap-around dielectric and control gate structure in the row direction with minimized variability in the dimensions of the structures. At least a portion of the high etch rate material is removed to form air gaps for isolation.

Abstract: Electrical isolation in non-volatile memory is provided by air gaps formed using sacrificial films of differing etch rates. A high etch rate material is formed in an isolation trench. Flowable chemical vapor deposition processes are used to form high etch rate films, and curing is performed to increase their etch rate. A low etch material is formed over the high etch rate material and provides a controlled etch back between charge storage regions in a row direction. A discrete low etch rate layer can be formed or the high etch rate material can be oxidized to form an upper region with a lower etch rate. A controlled etch back enables formation of a wrap-around dielectric and control gate structure in the row direction with minimized variability in the dimensions of the structures. At least a portion of the high etch rate material is removed to form air gaps for isolation.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. A blocking layer can be introduced to inhibit the formation of materials in the air gaps during subsequent process steps. The blocking layer may result in selective air gap formation or varying dimension of air gaps at cell areas relative to select gate areas in the memory. The blocking layer may result in a smaller vertical dimension for air gaps formed in the isolation regions at select gate areas relative to cell areas. The blocking layer may inhibit formation of air gaps at the select gate areas in other examples. Selective etching, implanting and different isolation materials may be used to selectively define air gaps.