Patents by Inventor Daisuke Minohara

Daisuke Minohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8110924
    Abstract: In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutoshi Nakamura, Norio Yasuhara, Tomoko Matsudai, Daisuke Minohara
  • Publication number: 20120013316
    Abstract: According to one embodiment, a DC-DC converter includes a mounting substrate and a semiconductor device. The semiconductor device includes a first switch element, a second switch element, a first interconnect layer receiving an input potential, a second interconnect layer connected with an inductor, a third interconnect layer receiving a reference potential, and a fourth interconnect layer connected with the inductor. These layers are disposed side by side in one direction on one layer. The mounting substrate includes a fifth interconnect pattern receiving an input potential and disposed adjacently on one side of a mounting region of the semiconductor device, a sixth interconnect pattern receiving a reference voltage and disposed adjacently on the one side of the mounting region, and a seventh interconnect pattern disposed adjacently on one other side opposite to the one side of the mounting region.
    Type: Application
    Filed: March 22, 2011
    Publication date: January 19, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazutoshi Nakamura, Daisuke Minohara
  • Publication number: 20110109295
    Abstract: According to one embodiment, a semiconductor device includes a first switching element and a second switching element. The first switching element has a first threshold voltage and a first gate electrode connected to a first gate wiring. The second switching element has a second threshold voltage and a second gate electrode connected to a second gate wiring. The second threshold voltage has a larger absolute value than the first threshold voltage. The second gate wiring has a larger resistance per unit length than the first gate wiring.
    Type: Application
    Filed: September 21, 2010
    Publication date: May 12, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke Minohara, Kazutoshi Nakamura
  • Publication number: 20110109287
    Abstract: According to one embodiment, a semiconductor package includes a chip, a plurality of bumps, a source frame, a drain frame, and a mold member. The chip has a lateral transistor formed inside the chip and has a top source electrode exposed on a first surface of the chip and a top drain electrode exposed on the first surface of the chip. The plurality of bumps are mounted on each of the top source electrode and the top drain electrode. The source frame is connected to the top source electrode through the bumps. The drain frame is connected to the top drain electrode through the bumps. The mold member embeds at least a part of each of the chip, the bumps, the source frame and the drain frame.
    Type: Application
    Filed: September 21, 2010
    Publication date: May 12, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazutoshi Nakamura, Daisuke Minohara
  • Publication number: 20090243087
    Abstract: In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 1, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazutoshi NAKAMURA, Nario YASUHARA, Tomoko MATSUDAI, Daisuke MINOHARA
  • Patent number: 6406800
    Abstract: A bent pipe for use in piping arrangement for transporting materials conaining solids, the bent pipe being prepared by subjecting to high-frequency bending work a straight blank pipe prepared by centrifugal casting and having a plurality of layers. The straight blank pipe comprises an outer layer made of a steel having high weldability, and an inner layer made of a high Cr cast iron containing at least Cr in an amount of 10 to 35 wt. % and having high wear resistance, the outer layer and the inner layer being metallurgically joined. Preferably, a barrier layer is provided between the outer layer and the inner layer for preventing an alloy component in each of the layers from diffusing into the other layer. The barrier layer is preferably about 10 to about 100 &mgr;m in thickness.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: June 18, 2002
    Assignee: Kubota Corporation
    Inventors: Makoto Ozaki, Daisuke Minohara