Abstract: According to one embodiment, a server device includes a memory and a processor. The memory stores verification information. The processor accepts a request to transmit a certificate number, generates information in which identification information of one of storage devices from which data is to be erased, a public key, a secret key, and the certificate number are associated with one another, transmits the certificate number, performs verification using an authenticator transmitted by the one storage device and verification information, generates, based on a result of the verification, an erasure certificate that includes the identification information and the certificate number and is signed using the secret key, and transmits the erasure certificate.

Abstract: According to one embodiment, a server device includes a memory and a processor. The memory stores verification information. The processor accepts a request to transmit a certificate number, generates information in which identification information of one of storage devices from which data is to be erased, a public key, a secret key, and the certificate number are associated with one another, transmits the certificate number, performs verification using an authenticator transmitted by the one storage device and verification information, generates, based on a result of the verification, an erasure certificate that includes the identification information and the certificate number and is signed using the secret key, and transmits the erasure certificate.

Abstract: A storage apparatus includes a storage unit having plural regions including a first region and a second region, an interface unit configured to receive from an external device an access request for access to the first region, and a controller configured to control the storage unit to store in the second region information indicating that the access request has been received and executed.

Abstract: According to one embodiment, according to one embodiment, a memory system includes a first memory, a second memory, an interface, a managing unit, and a control unit. The second memory stores data read out from the first memory. The interface receives a read command. The managing unit manages a corresponding relationship of a first address included in the read command and a second address. The second address is an address indicating a position in the first memory where data designated by the first address is stored. The control unit acquires a plurality of second addresses corresponding to a sequential first address range including the first address in a case where the read command is received, and determine an amount of data to be read out from the first memory to the second memory based on whether the plurality of second addresses is sequential or not.

Abstract: According to one embodiment, according to one embodiment, a memory system includes a first memory, a second memory, an interface, a managing unit, and a control unit. The second memory stores data read out from the first memory. The interface receives a read command. The managing unit manages a corresponding relationship of a first address included in the read command and a second address. The second address is an address indicating a position in the first memory where data designated by the first address is stored. The control unit acquires a plurality of second addresses corresponding to a sequential first address range including the first address in a case where the read command is received, and determine an amount of data to be read out from the first memory to the second memory based on whether the plurality of second addresses is sequential or not.