Abstract: According to an embodiment, a method includes receiving a query, and selecting one of first objects on the basis of the query and a neural network model. Each of the first objects is associated with one or more pieces of first data in a group of first data stored on a first memory. The method further includes calculating a metric of a distance between the query and one or more pieces of second data. The one or more pieces of second data are one or more pieces of first data associated with a second object. The second object is the one of the first objects having been selected. The method further includes identifying third data on the basis of the metric of the distance. The third data is first data closest to the query in the group of the first data.

Abstract: An arithmetic apparatus used for a neural network includes a plurality of digital-time conversion circuits connected in series and a time-digital conversion circuit connected to a last digital-time conversion circuit in the series. Each of the digital-time conversion circuits is configured to delay a first input time signal by a variable amount, delay a second input time signal by a fixed amount, and output the delayed first and second input time signals respectively as either first and second output time signals or second and first output time signals, in accordance with the input data. The time-digital conversion circuit is configured to generate a digital output signal by comparing first and second output time signals from the last digital-time conversion circuit.

Abstract: An arithmetic operation device is provided that removes a part of parameters of a predetermined number of parameters from a first machine learning model which includes the predetermined number of parameters and is trained so as to output second data corresponding to input first data, determines the number of bits of a weight parameter according to required performance related to an inference to generate a second machine learning model, and acquires data output from the second machine learning model so as to correspond to the input first data with a smaller computational complexity than the first machine learning model.

Abstract: According to one embodiment, an apparatus includes: an interface circuit configured to receive first data items respectively relating to documents and a second data item relating to a question; and a processor configured to process the first and second data items, wherein the processor is configured to: extract first named entities respectively from the first data items and extract a second named entity from the second data item; generate first vectors respectively relating to the first data items and the corresponding first named entities; generate a second vector relating to the second data item and the second named entity; calculate a similarity between each of the first vectors and the second vector; and acquire a third data item relating to an answer retrieved from the first data items based on a result of calculating the similarity.

Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

Abstract: According to one embodiment, an information processing device includes: an encoder including a first layer and a second layer which are coupled in series; and a decoder. The encoder is configured to: generate, based on first data, a first key and a first value in the first layer, and a second key and a second value in the second layer; and generate, based on second data different from the first data, a first query in the first layer, and a second query in the second layer. The decoder is configured to: generate third data which is included in the first data and is not included in the second data, based on the first key, the first value, the first query, the second key, the second value, and the second query.

Abstract: According to one embodiment, in a calculation system, a plurality of multiplying elements is arrayed to form a plurality of rows and a plurality of columns and are configured to multiply a plurality of first signals by respective weights to generate a plurality of calculation results and are configured to calculate a sum of calculation results in each column among the plurality of calculation results to generate a plurality of second signals individually for the plurality of columns. A first processing circuit is configured to receive the plurality of second signals generated by the adding elements, and to extract values corresponding to certain second signals among the plurality of second signals. A second processing circuit including a plurality of address circuits corresponding to the plurality of second signals, and configured to selectively enable address circuits corresponding to the certain second signals among the plurality of address circuits.

Abstract: An information processing device includes a first memory, a second memory, and a processor. The first memory stores clusters into which first data segments are grouped according to distances among the first data segments and each including one or more first data segments. The second memory is operable at a higher speed than the first memory and stores second data segments corresponding one-to-one to the clusters. The processor receives an input query and identify a third data segment being one of the second data segments closest to the query, from the second data segments. The processor collectively reads, from the first memory, one or more first data segments included in a cluster corresponding to the third data segment among the clusters, and identify a fourth data segment being one of the first data segments closest to the query from the one or more first data segments for output.

Abstract: According to one embodiment, an information processing method includes: calculating a first feature amount of query data in a first field; calculating first similarity degrees between the first feature amount and second feature amounts in the first field; obtaining, based on the first similarity degrees, third feature amounts in a second field that are associated with feature amounts selected from the second feature amounts, the second field being different from the first field; calculating fourth feature amounts in the second field, for choices concerning the query data; calculating second similarity degrees between the third feature amounts and the fourth feature amounts; and selecting, based on the second similarity degrees, an answer to the query data among answer candidates corresponding to the third feature amounts.

Abstract: An engine includes a combustion chamber, a cylinder head, an intake valve, a partition wall plate, and a tumble valve. The cylinder head includes an intake port that communicates with the combustion chamber. The intake valve includes a head configured to open and close an open end of the intake port. The partition wall plate partitions the intake port into first and second passages. The tumble valve is configured to open and close either one of the first passage and the second passage. A cross sectional shape of the partition wall plate is defined on a basis of a shape of a gap that is surrounded by a contour of the head and a contour of the open end, as viewed in a reference direction. The reference direction is a direction from a reference point in the intake port to a gap between the open end and the head.

Abstract: According to one embodiment, in a semiconductor integrated circuit, the plurality of storage devices are arranged in a form of a plurality of rows. Each of the storage devices are configured to store a bit position value of a weight of multiple bits. The plurality of multiplication circuits are arranged in a form of a plurality of rows and are configured to multiply a plurality of input voltages by the weight of multiple bits to generate a plurality of multiplication results. The one or more capacitive devices are configured to accumulate charges corresponding to the plurality of multiplication results. The adder circuit are configured to generate an output voltage corresponding to the total value of the charges accumulated in the one or more capacitive devices. The plurality of input voltages have different amplitudes. Each of the input voltages is associated with a corresponding bit position of the weight.

Abstract: According to one embodiment, an information processing method includes performing, in an intermediate layer of a deep neural network, a forward propagation using a first parameter and based on a first input value represented by a first bit number; performing quantization to produce a second input value represented by a second bit number smaller than the first bit number, and storing the produced second input value in the memory; calculating a second parameter based on a result of an operation using the second input value stored in the memory and a value obtained by the forward propagation, the second parameter being an update of the first parameter and for use in the learning process; and determining a condition for the quantization based on a gradient difference obtained in said calculating the second parameter.

Abstract: According to one embodiment, an information processing device includes: an encoder including a first layer and a second layer which are coupled in series; and a decoder. The encoder is configured to: generate, based on first data, a first key and a first value in the first layer, and a second key and a second value in the second layer; and generate, based on second data different from the first data, a first query in the first layer, and a second query in the second layer. The decoder is configured to: generate third data which is included in the first data and is not included in the second data, based on the first key, the first value, the first query, the second key, the second value, and the second query.

Abstract: According to one embodiment, in a semiconductor integrated circuit, a second switch has a first end connected to a first end of a capacitive element and a second end connected to a node of a reference potential. A third switch has a first end connected to the first end of the capacitive element and a second end connected to an input node of an amplifier circuit. A control circuit maintains the second switch in an on state while maintaining a first and the third switches in an off state in a first period and maintains the first switch in an on state while maintaining the second and third switches in an off state in a second period after the first period. End timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal from a global circuit.

Abstract: According to one embodiment, a processor is configured to calculate a calculation amount in inference time of a neural network, using a result of summing, with respect to a group to which quantization is applied, products of the number of product-sum operations and bit widths of weight for the product-sum operations in the neural network. Then, the processor is configured to optimize a value of the weight and a quantization step size to minimize the recognition error by the neural network based on the calculated calculation amount, and execute computing about the neural network based on the optimized weight and the quantization step size.

Abstract: According to an embodiment, an arithmetic device configured to execute an operation related to a neural network approximately calculates similarities between a first vector and a plurality of second vectors. Further, the arithmetic device selects, among the plurality of second vectors, a plurality of third vectors whose similarities are equal to or greater than a threshold. Furthermore, the arithmetic device also calculates similarities between the first vector and the selected plurality of third vectors.

Abstract: According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.

Abstract: According to one embodiment, an arithmetic apparatus includes a non-volatile first memory, a second memory, and a controller. The first memory stores a model to be trained. The second memory has a smaller storage capacity than the first memory. The controller executes learning processing that updates a first parameter of the model based on a loss value obtained by inputting training data into the model stored in the first memory, and stores cumulative update information indicating a difference of the first parameter before and after the update in the second memory. In addition, the controller executes the learning processing using a second parameter in which the cumulative update information stored in the second memory is reflected in the first parameter read from the model stored in the first memory, and stores a difference between a third parameter obtained by updating the second parameter and the first parameter, in the second memory as the cumulative update information.

Abstract: An engine includes a combustion chamber, a cylinder head, an intake valve, a partition wall plate, and a tumble valve. The cylinder head includes an intake port that communicates with the combustion chamber. The intake valve includes a head configured to open and close an open end of the intake port. The partition wall plate partitions the intake port into first and second passages. The tumble valve is configured to open and close either one of the first passage and the second passage. A cross sectional shape of the partition wall plate is defined on a basis of a shape of a gap that is surrounded by a contour of the head and a contour of the open end, as viewed in a reference direction. The reference direction is a direction from a reference point in the intake port to a gap between the open end and the head.

Abstract: According to one embodiment, a processing device includes: a first circuit configured to execute first processing using a first matrix to first data of a size of 5×5 within input data to generate second data; a second circuit configured to execute second processing using a second matrix to third data of a size of 3×3 to generate fourth data; a third circuit configured to execute a product-sum operation on the second data and the fourth data; and a fourth circuit configured to execute third processing using a third matrix on a result of the product-sum operation on the second data and the fourth data to obtain a first value corresponding to a result of a product-sum operation on the first data and the third data.