Patents by Inventor Daisuke Nakamata

Daisuke Nakamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9662805
    Abstract: A method of resuming operation of a wire saw in which slicing of a workpiece is suspended due to a wire break, including processes of: imparting axial reciprocating motion to a wire while supplying a new line of the wire; and slicing the workpiece into wafers by moving the workpiece downwardly to press the workpiece against the reciprocating wire while supplying a slicing slurry to the wire, the method includes: repairing the broken wire after suspending the slicing of the workpiece before resuming the slicing of the workpiece; and preparing for the slicing in that a diameter of the repaired wire at a position at which the workpiece is to be sliced is matched to the diameter of the wire just before occurrence of the wire break. The method can inhibit the formation of grooves in wafers sliced after the resumption and reduce low-quality production wafers.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: May 30, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Atsuo Uchiyama, Hisakazu Takano, Hitoshi Sejimo, Yukio Hijirisawa, Daisuke Nakamata
  • Publication number: 20150328800
    Abstract: A method of resuming operation of a wire saw in which slicing of a workpiece is suspended due to a wire break, including processes of: imparting axial reciprocating motion to a wire while supplying a new line of the wire; and slicing the workpiece into wafers by moving the workpiece downwardly to press the workpiece against the reciprocating wire while supplying a slicing slurry to the wire, the method includes: repairing the broken wire after suspending the slicing of the workpiece before resuming the slicing of the workpiece; and preparing for the slicing in that a diameter of the repaired wire at a position at which the workpiece is to be sliced is matched to the diameter of the wire just before occurrence of the wire break. The method can inhibit the formation of grooves in wafers sliced after the resumption and reduce low-quality production wafers.
    Type: Application
    Filed: December 6, 2013
    Publication date: November 19, 2015
    Inventors: Atsuo UCHIYAMA, Hisakazu TAKANO, Hitoshi SEJIMO, Yukio HIJIRISAWA, Daisuke NAKAMATA
  • Patent number: 8210906
    Abstract: A wafer slicing method includes winding a wire around rollers and pressing the wire against an ingot while supplying slurry to the rollers. A previously conducted experiment provides a supply temperature profile of the slurry during the slicing process and the relationship to the axial displacement of the rollers. This relationship is used to implement slurry delivery during the slicing process. The resultant wafers are bowed in a uniform direction. This slicing method provides excellent reproducibility in addition to producing wafers that are bowed in a uniform direction.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: July 3, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Oishi, Daisuke Nakamata
  • Patent number: 8167681
    Abstract: The present invention provides a slicing method comprising winding a wire around a plurality of grooved rollers and pressing the wire against an ingot to be sliced into wafers while supplying a slurry for slicing to the grooved rollers and causing the wire to travel, wherein a supply temperature of the slurry for slicing is controlled, and slicing is performed in such a manner that the supply temperature of the slurry for slicing and a temperature of the ingot become at least 30° C. or above at end of slicing the ingot. As a result, there is provided the slicing method that can alleviate precipitous cooling of an ingot in the time close to end of slicing the ingot and thereby suppress production of a nano-topography when slicing the ingot by using a wire saw.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: May 1, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Oishi, Daisuke Nakamata
  • Patent number: 7988530
    Abstract: The present invention provides a slicing method comprising winding a wire around a plurality of grooved rollers and pressing the wire against an ingot to be sliced into wafers while supplying a slurry for slicing to the grooved rollers and causing the wire to travel, wherein a cooling speed of the ingot when a slicing depth is equal to or above ? of a diameter is controlled to perform slicing by supplying a slurry for adjusting an ingot temperature to the ingot independently from the slurry for slicing while controlling a supply temperature only in a period from the moment that the slicing depth of the ingot reaches at least ? of the diameter to end of slicing. As a result, the slicing method is provided, in which rapid cooling of the ingot in the time close to end of slicing the ingot can be alleviated when a wire saw is used to slice the ingot, and generation of a nano-topography can be thereby suppressed and further high quality wafers having a uniform thickness are obtained by slicing.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 2, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Oishi, Daisuke Nakamata
  • Patent number: 7810383
    Abstract: The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: October 12, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Keiichi Okabe, Hisakazu Takano, Daisuke Nakamata
  • Publication number: 20100037881
    Abstract: The present invention provides a slicing method comprising winding a wire around a plurality of grooved rollers and pressing the wire against an ingot to be sliced into wafers while supplying a slurry for slicing to the grooved rollers and causing the wire to travel, wherein a supply temperature of the slurry for slicing is controlled, and slicing is performed in such a manner that the supply temperature of the slurry for slicing and a temperature of the ingot become at least 30° C. or above at end of slicing the ingot. As a result, there is provided the slicing method that can alleviate precipitous cooling of an ingot in the time close to end of slicing the ingot and thereby suppress production of a nano-topography when slicing the ingot by using a wire saw.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 18, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Oishi, Daisuke Nakamata
  • Publication number: 20090288530
    Abstract: There is provided a slicing method including winding a wire around a plurality of grooved rollers and pressing the wire against an ingot to be sliced into wafers while supplying a slurry for slicing to the grooved rollers and causing the wire to travel, in which a test of slicing the ingot while supplying the slurry for slicing to the grooved rollers and controlling a supply temperature thereof is previously conducted to examine a relationship between an axial displacement of the grooved rollers and a supply temperature of the slurry for slicing, a supply temperature profile of the slurry for slicing is set based on the relationship between an axial displacement of the grooved rollers and a supply temperature of the slurry for slicing, and the slurry for slicing is supplied based on the supply temperature profile to slice the ingot while controlling an axial displacement of the grooved rollers and to uniform Sori of all wafers to be sliced out in one direction.
    Type: Application
    Filed: August 22, 2007
    Publication date: November 26, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD
    Inventors: Hiroshi Oishi, Daisuke Nakamata
  • Publication number: 20090253352
    Abstract: The present invention provides a slicing method comprising winding a wire around a plurality of grooved rollers and pressing the wire against an ingot to be sliced into wafers while supplying a slurry for slicing to the grooved rollers and causing the wire to travel, wherein a cooling speed of the ingot when a slicing depth is equal to or above ? of a diameter is controlled to perform slicing by supplying a slurry for adjusting an ingot temperature to the ingot independently from the slurry for slicing while controlling a supply temperature only in a period from the moment that the slicing depth of the ingot reaches at least ? of the diameter to end of slicing. As a result, the slicing method is provided, in which rapid cooling of the ingot in the time close to end of slicing the ingot can be alleviated when a wire saw is used to slice the ingot, and generation of a nano-topography can be thereby suppressed and further high quality wafers having a uniform thickness are obtained by slicing.
    Type: Application
    Filed: August 8, 2007
    Publication date: October 8, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Oishi, Daisuke Nakamata
  • Publication number: 20080166823
    Abstract: The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.
    Type: Application
    Filed: March 24, 2006
    Publication date: July 10, 2008
    Inventors: Keiichi Okabe, Hisakazu Takano, Daisuke Nakamata