Patents by Inventor Daisuke Namihira

Daisuke Namihira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10044558
    Abstract: A disclosed switch includes: plural ports; a first unit that applies profile associated with identification data to a port of the plural ports, upon receiving a message, which includes the identification data of profile relating to the another apparatus, through a first link in a situation that another apparatus connected to the port through the first link is connected to another switch through a second link and the first and second link are virtually integrated; a second unit that generates information including a first identifier of the profile and a second identifier of the first and second links virtually integrated, and transmits the information to the another switch, upon receiving the message; and a third unit that applies profile associated with a third identifier to the port when that profile has not been applied, upon receiving the third identifier of the profile and the second identifier from the another switch.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 7, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Daisuke Namihira
  • Patent number: 9742698
    Abstract: A disclosed switch includes: plural ports each of which is connected to another apparatus; a determination unit that determines, for each of the plural ports, whether the port is connected to one of plural switches integrated logically; and a setting unit that sets, for each of the plural ports, a port type or propriety of use based on a result of determination by the determination unit.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 22, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Daisuke Namihira
  • Patent number: 9628410
    Abstract: A disclosed switch includes: ports that include a first port to be connected to another switch included in a first domain that includes plural switches to be virtually integrated, and a second port that is other than the first port; a first processing unit configured to obtain data of a switch included in the first domain through the first port; and a second processing unit configured to obtain data of switches included in a second domain that is adjacent to the first domain through the second port and obtain data of switches included in the second domain from the another switch included in the first domain to identify, from among the ports, plural ports that are connected to the second domain, perform a setting for the identified plural ports, and perform a first processing to make plural domains that include the first and second domains a tree structure.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: April 18, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Daisuke Namihira
  • Patent number: 9515846
    Abstract: A disclosed switch includes: a first applying unit that applies a setting of a virtual subnetwork to a first port that is connected to an external apparatus, upon detecting an instruction to apply the setting to the first port; and a second applying unit that applies, upon detecting that the setting was applied to the first port in the switch or other switches, the setting to a second port that is connected to an external network and is associated with the first port in advance.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: December 6, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Daisuke Namihira
  • Patent number: 9270519
    Abstract: An address translation device includes a receiver that receives a packet that is from a communication apparatus on a private network to a communication apparatus on a global network; an address determiner that determines whether a destination address of a first packet received by the receiver matches a destination address of a second packet that was received before the first packet; a translator that when the address determiner makes a determination of no matching, translates a source private address of the first packet to a source global address that has been allocated to the second packet; and a transmitter that transmits the first packet that has been translated by the translator.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 23, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Daisuke Namihira
  • Publication number: 20150372862
    Abstract: A disclosed switch includes: plural ports; a first unit that applies profile associated with identification data to a port of the plural ports, upon receiving a message, which includes the identification data of profile relating to the another apparatus, through a first link in a situation that another apparatus connected to the port through the first link is connected to another switch through a second link and the first and second link are virtually integrated; a second unit that generates information including a first identifier of the profile and a second identifier of the first and second links virtually integrated, and transmits the information to the another switch, upon receiving the message; and a third unit that applies profile associated with a third identifier to the port when that profile has not been applied, upon receiving the third identifier of the profile and the second identifier from the another switch.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Inventor: Daisuke Namihira
  • Publication number: 20150326502
    Abstract: A disclosed switch includes: plural ports each of which is connected to another apparatus; a determination unit that determines, for each of the plural ports, whether the port is connected to one of plural switches integrated logically; and a setting unit that sets, for each of the plural ports, a port type or propriety of use based on a result of determination by the determination unit.
    Type: Application
    Filed: July 23, 2015
    Publication date: November 12, 2015
    Inventor: Daisuke Namihira
  • Publication number: 20150295730
    Abstract: A disclosed switch includes: a first applying unit that applies a setting of a virtual subnetwork to a first port that is connected to an external apparatus, upon detecting an instruction to apply the setting to the first port; and a second applying unit that applies, upon detecting that the setting was applied to the first port in the switch or other switches, the setting to a second port that is connected to an external network and is associated with the first port in advance.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 15, 2015
    Inventor: Daisuke Namihira
  • Patent number: 8832332
    Abstract: By referring to a receiving connection information table stored in a memory, a receiving assignment CPU assigns packets to parallel processing CPUs in such a manner that the packets received from the same connection are subjected to a receiving process by a corresponding parallel processing CPU. Each parallel processing CPU identifies the input QoS of a packet and notifies a QoS processing CPU, corresponding to that identified input QoS, of the packet. Each QoS processing CPU is arranged so that it corresponds to a QoS processing queue group in the memory and performs a QoS process on this QoS processing queue group.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Limited
    Inventor: Daisuke Namihira
  • Publication number: 20140233581
    Abstract: A disclosed switch includes: ports that include a first port to be connected to another switch included in a first domain that includes plural switches to be virtually integrated, and a second port that is other than the first port; a first processing unit configured to obtain data of a switch included in the first domain through the first port; and a second processing unit configured to obtain data of switches included in a second domain that is adjacent to the first domain through the second port and obtain data of switches included in the second domain from the another switch included in the first domain to identify, from among the ports, plural ports that are connected to the second domain, perform a setting for the identified plural ports, and perform a first processing to make plural domains that include the first and second domains a tree structure.
    Type: Application
    Filed: December 16, 2013
    Publication date: August 21, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Daisuke NAMIHIRA
  • Publication number: 20120207173
    Abstract: An address translation device includes a receiver that receives a packet that is from a communication apparatus on a private network to a communication apparatus on a global network; an address determiner that determines whether a destination address of a first packet received by the receiver matches a destination address of a second packet that was received before the first packet; a translator that when the address determiner makes a determination of no matching, translates a source private address of the first packet to a source global address that has been allocated to the second packet; and a transmitter that transmits the first packet that has been translated by the translator.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Daisuke NAMIHIRA
  • Patent number: 7929550
    Abstract: Information (service information) about service contents provided by servers is registered or updated by each of routing nodes by exchanging said information through use of a routing protocol used in controlling a path among the routing nodes. The routing node selectively changes address information about a service access request on the basis of the service information owned by the routing node, to thus route the service access request to an optimal destination. Thereby, concentration of load to a specific service can be efficiently dispersed.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Limited
    Inventors: Daisuke Namihira, Yasunori Terasaki
  • Publication number: 20100293280
    Abstract: A packet processing device includes a memory unit that includes a plurality of areas each corresponding to a type of communication that is used for packet transmission, a plurality of processing units that is provided in correspondence with the type of communication and performs a process on the packet, an allocating unit that allocates a processing target packet to the processing unit corresponding to the type of communication that is used for transmission of the processing target packet, an assigning unit that assigns the area corresponding to the type of communication that is used for transmission of the processing target packet to the processing unit to which the processing target packet is allocated, and a storage unit that stores information on the process of the processing target packet and information on the type of communication that is used for transmission of the processing target packet in the assigned area.
    Type: Application
    Filed: July 20, 2010
    Publication date: November 18, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Daisuke Namihira
  • Publication number: 20100281190
    Abstract: By referring to a receiving connection information table stored in a memory, a receiving assignment CPU assigns packets to parallel processing CPUs in such a manner that the packets received from the same connection are subjected to a receiving process by a corresponding parallel processing CPU. Each parallel processing CPU identifies the input QoS of a packet and notifies a QoS processing CPU, corresponding to that identified input QoS, of the packet. Each QoS processing CPU is arranged so that it corresponds to a QoS processing queue group in the memory and performs a QoS process on this QoS processing queue group.
    Type: Application
    Filed: July 7, 2010
    Publication date: November 4, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Daisuke Namihira
  • Patent number: 7561516
    Abstract: In a network of a variable length packet system, a bps calculator colors an inputted packet based on a peak bandwidth or a committed bandwidth of a data bit number per unit time for every flow and a packet length of the inputted packet, a pps calculator colors the inputted packet based on a peak bandwidth or a committed bandwidth of a packet number per unit time for every flow and a packet number of the inputted packet, and one of a color of packet to be discarded, a color of packet to be passed and a color of packet to be discarded with a probability, within the colors obtained by colorings at both calculators is determined by a color selector.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: July 14, 2009
    Assignee: Fujitsu Limited
    Inventors: Junichi Ehara, Daisuke Namihira, Masao Yoshikawa
  • Patent number: 7447221
    Abstract: A communication apparatus to be used between first and second communication groups, each including one or more communication terminals, that perform communications by different types of communication protocols capable of embedding address information, comprises a first storage unit storing a destination address, and tunnel identification information for the first communication group when a packet transmitted from the second communication group is registered; a destination retrieval unit which determines whether a destination address extracted from the received packet is registered in the first storage unit; a second storage unit, storing information indicating whether the route designated by the tunnel identification information is constructible by a private address or by a global address; an encapsulation processing unit which extracts the address information for the first communication group from the destination address; and a control unit controlling whether the encapsulation is to be in accordance with th
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: November 4, 2008
    Assignee: Fujitsu Limited
    Inventor: Daisuke Namihira
  • Publication number: 20080250496
    Abstract: A frame relay device includes a table where an entry containing a combination of an MAC address and an IP address is registered to be used in the frame relay processing of a local device. Moreover, the frame relay device includes judgment means for searching the table by the transmission origin MAC address and the transmission origin IP address contained in the frame received and judging whether the combination of the transmission origin addresses is registered as a relay object in the layer 3. Furthermore, the frame relay device includes layer 3 relay processing means for performing layer 3 relay processing only for the frame which has been judged to contain the combination of the transmission origin addresses as a relay object.
    Type: Application
    Filed: October 7, 2003
    Publication date: October 9, 2008
    Inventor: Daisuke Namihira
  • Publication number: 20080194198
    Abstract: In a data transfer circuit, particular data information specifying, from among received data, particular data which circulates over a network within a certain time is stored in a particular data information storing portion, and the particular data information corresponding to the received data is retrieved from the particular data information storing portion. The particular data information registered in the particular data information storing portion is initialized after the lapse of a certain period from the reception of the particular data corresponding to the registered particular data information, and the received data is abandoned when the particular data information corresponding to the received data is retrieved from the particular data information storing portion. A data transfer apparatus, a data transfer method, and a control program are also provided.
    Type: Application
    Filed: February 13, 2008
    Publication date: August 14, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Daisuke NAMIHIRA
  • Patent number: 7409458
    Abstract: A network system comprising a transmission medium coupling a plurality of devices on the network, a plurality of relay devices connected to the transmission medium, each relay device operable to apply filtering on data from the network and transmits frames, each relay device comprising command process division operable to generate and parse commands that include filtering information relating the sharing of filtering information on the network, and when filtering sharing conditions are applied, register filtering information on its own device and apply a protocol to relay to an adjacent device if filtering information sent from an adjacent device through the filtering sharing conditions has a destination address, if a port that received the filtering information from the adjacent matches a relay destination port of the destination address, and if there is only one relay destination port for the destination address, register a receiving port of the filtering information as a destination port, if there is no de
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: August 5, 2008
    Assignee: Fujitsu Limited
    Inventor: Daisuke Namihira
  • Patent number: 7206898
    Abstract: The invention relates to a content-addressable memory. An object of the invention is to make the content-addressable memory adaptable to various apparatuses and systems having different configurations without substantially altering the basic configuration thereof. The content-addressable memory includes a storage section having a plurality of storage areas for storing respective plural pieces of information; an ancillary storage section having a plurality of ancillary storage areas that correspond to the plurality of storage areas and store priority ranks that are assigned to the respective plurality of storage areas; and a controlling section for outputting, when at least one of the storage areas stores therein information matching with an externally supplied word, pointers of all or part of the at least one of the storage areas in descending order of priority ranks that are stored in ancillary storage areas corresponding to the at least one of storage areas.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 17, 2007
    Assignee: Fujitsu Limited
    Inventors: Kimihito Matsumoto, Takashi Iino, Yasunori Terasaki, Daisuke Namihira, Ken Aoyama