Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers, the electrode layers and the insulating layers being alternately stacked, and a memory film extending in a stacking direction in the stacked body. The memory film includes an oxide film facing the insulating layers, a block insulating film facing the electrode layers and the oxide film, and a charge storage film facing the block insulating film. The block insulating film has a larger thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers, and the charge storage film has a smaller thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers.

Abstract: A semiconductor manufacturing apparatus according to an embodiment includes: a chamber that houses a semiconductor substrate; and a plurality of coils provided on a lateral surface of the chamber. The chamber has a first spatial region enclosed above the semiconductor substrate by a first coil that is one of the plurality of coils, a first gas introduction port communicating with the first spatial region, a second spatial region enclosed by a second coil that is different from the first coil among the plurality of coils, and a second gas introduction port communicating with the second spatial region.

Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.

Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.

Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises: a lid member; a support member; an oxidation resistant member; and an oxidizing system gas introducing member. The lid member is opposed to a surface of a semiconductor substrate. The support member supports the lid member. The oxidation resistant member is opposed to a back of the semiconductor substrate. The oxidizing system gas introducing member introduces an oxidizing system gas that oxidizes the back of the semiconductor substrate.

Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises: a lid member; a support member; an oxidation resistant member; and an oxidizing system gas introducing member. The lid member is opposed to a surface of a semiconductor substrate. The support member supports the lid member. The oxidation resistant member is opposed to a back of the semiconductor substrate. The oxidizing system gas introducing member introduces an oxidizing system gas that oxidizes the back of the semiconductor substrate.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including: a first electrode layer including a first portion and a second portion thicker than the first portion in stacking direction of the stacked body; and an insulating layer provided between the first electrode layer and the substrate; a semiconductor film provided in the stacked body and extending in the stacking direction; a charge storage film provided between the semiconductor film and the first electrode layer; and a first intermediate insulating film provided between the charge storage film and the first electrode layer. The distance between the semiconductor film and the second portion is shorter than the distance between the semiconductor film and the first portion. The first intermediate insulating film extends in the stacking direction.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode films and a plurality of insulating films, the plurality of electrode films and the plurality of insulating films being alternately stacked on each other, a semiconductor pillar extending in a stacking direction of the stacked body, and a charge storage film provided between the electrode films and the semiconductor pillar and extending linearly in the stacking direction of the stacked body. A stacking-direction width of an edge portion of the electrode films on side of the semiconductor pillar is shorter than a stacking-direction width of the electrode films other than the edge portion of the electrode films.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.

Abstract: In a battery pack (1),a current loop between the positive and negative electrode plates of an electrode assembly passes points P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13 and P14 in this order. A line that connects P2 to P3 intersects a line that connects P11 to P12 in the part where the loop passes a sealing plate (12), which is arranged on the top of a battery unit (10). The loop can be divided into loop parts B1 and B2. The part B1 is formed on the exterior side of the battery unit, and extends from the intersection A through a circuit board (20) back to the intersection A. The part B2 is formed on the interior side of the battery unit relative to the intersection A. The current flows counterclockwise and clockwise in the parts B1 and B2, respectively.

Abstract: In a battery pack (1), a current loop between the positive and negative electrode plates of an electrode assembly passes points P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13 and P14 in this order. A line that connects P2 to P3 intersects a line that connects P11 to P12 in the part where the loop passes a sealing plate (12), which is arranged on the top of a battery unit (10). The loop can be divided into loop parts B1 and B2. The part B1 is formed on the exterior side of the battery unit, and extends from the intersection A through a circuit board (20) back to the intersection A. The part B2 is formed on the interior side of the battery unit relative to the intersection A. The current flows counterclockwise and clockwise in the parts B1 and B2, respectively.

Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.

Abstract: The present invention relates to an active energy beam-curable ink comprising polymerizable monomers, wherein relative to the total of all the polymerizable monomers, the polymerizable monomers comprise from 95 to 99.99% by weight of a monofunctional monomer and from 0.01 to 5% by weight of a polyfunctional monomer, and a cured film of thickness 10 ?m formed using the active energy beam-curable ink exhibits a drawing ability exceeding 120% when stretched at a temperature of 170° C. at a strain rate of 2/min.

Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, forming the second insulating film comprises forming a lower insulating film containing oxygen and a metal element, thermally treating the lower insulating film in an atmosphere containing oxidizing gas, and forming an upper insulating film on the thermally treated lower insulating film using film forming gas containing at least one of hydrogen and chlorine.

Abstract: A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.