Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers, the electrode layers and the insulating layers being alternately stacked, and a memory film extending in a stacking direction in the stacked body. The memory film includes an oxide film facing the insulating layers, a block insulating film facing the electrode layers and the oxide film, and a charge storage film facing the block insulating film. The block insulating film has a larger thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers, and the charge storage film has a smaller thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers, the electrode layers and the insulating layers being alternately stacked, and a memory film extending in a stacking direction in the stacked body. The memory film includes an oxide film facing the insulating layers, a block insulating film facing the electrode layers and the oxide film, and a charge storage film facing the block insulating film. The block insulating film has a larger thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers, and the charge storage film has a smaller thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers.

Abstract: The present invention eliminates a dead space between a gasket and flanges and the present invention is an annular gasket 30 attached between planar seal surfaces 12x of opposing flange portions 12, in which steps 30d are formed between radially inner surfaces 30b continuous with an inner peripheral surface 30a and radially outer surfaces 30c, each radially inner surface 30b is located axially outward the corresponding radially outer surface 30c, the radially inner surface 30b and the radially outer surface 30c each have a planar shape orthogonal to an axial direction, and each radially outer surface 30c comes into contact with the corresponding seal surface 12x after each radially inner surface 30b comes into contact with the corresponding seal surface 12x.

Abstract: An image point cloud data processing device includes processing circuitry to detect a plurality of image feature points in a reference object included in image data generated by a camera and to calculate image representative positions as a plurality of three-dimensional positions representing the reference object based on the plurality of image feature points; to detect an in-region point cloud, as a three-dimensional point cloud existing in a detection region determined based on the image representative positions, in three-dimensional point cloud data generated by a distance measurement sensor and indicating a three-dimensional point cloud, and to detect a representative point cloud representing the reference object based on the in-region point cloud; and to make the image data and the three-dimensional point cloud data be data in a common coordinate system based on the image representative positions and the representative point cloud.

Abstract: A semiconductor device includes a stack including a conductor layer and an insulator layer, a block insulating layer, a channel layer, a charge storage layer provided between the block insulating layer and the channel layer, and a tunnel layer provided between the charge storage layer and the channel layer, where the charge storage layer includes a first charge storage layer containing Si, N and at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P, a second charge storage layer containing Si and N, in which Si is contained at a second concentration higher than a first concentration that is a concentration of Si in the first charge storage layer, and provided between the first charge storage layer and the tunnel layer, and a dielectric layer containing at least one of silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or aluminum oxide (AlOx), and provided between the first charge storage layer and the second charge storage layer.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked film in which a plurality of silicon oxide layers, one of which having a film density of 2.3 g/cm3 or more, and a plurality of conductive layers, are alternately stacked in a first direction, and a memory pillar that penetrates the stacked film in the first direction, wherein a plurality of memory cells is provided in the memory pillar.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers, the electrode layers and the insulating layers being alternately stacked, and a memory film extending in a stacking direction in the stacked body. The memory film includes an oxide film facing the insulating layers, a block insulating film facing the electrode layers and the oxide film, and a charge storage film facing the block insulating film. The block insulating film has a larger thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers, and the charge storage film has a smaller thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers.

Abstract: A semiconductor manufacturing apparatus according to an embodiment includes: a chamber that houses a semiconductor substrate; and a plurality of coils provided on a lateral surface of the chamber. The chamber has a first spatial region enclosed above the semiconductor substrate by a first coil that is one of the plurality of coils, a first gas introduction port communicating with the first spatial region, a second spatial region enclosed by a second coil that is different from the first coil among the plurality of coils, and a second gas introduction port communicating with the second spatial region.

Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.

Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.

Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises: a lid member; a support member; an oxidation resistant member; and an oxidizing system gas introducing member. The lid member is opposed to a surface of a semiconductor substrate. The support member supports the lid member. The oxidation resistant member is opposed to a back of the semiconductor substrate. The oxidizing system gas introducing member introduces an oxidizing system gas that oxidizes the back of the semiconductor substrate.

Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises: a lid member; a support member; an oxidation resistant member; and an oxidizing system gas introducing member. The lid member is opposed to a surface of a semiconductor substrate. The support member supports the lid member. The oxidation resistant member is opposed to a back of the semiconductor substrate. The oxidizing system gas introducing member introduces an oxidizing system gas that oxidizes the back of the semiconductor substrate.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including: a first electrode layer including a first portion and a second portion thicker than the first portion in stacking direction of the stacked body; and an insulating layer provided between the first electrode layer and the substrate; a semiconductor film provided in the stacked body and extending in the stacking direction; a charge storage film provided between the semiconductor film and the first electrode layer; and a first intermediate insulating film provided between the charge storage film and the first electrode layer. The distance between the semiconductor film and the second portion is shorter than the distance between the semiconductor film and the first portion. The first intermediate insulating film extends in the stacking direction.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode films and a plurality of insulating films, the plurality of electrode films and the plurality of insulating films being alternately stacked on each other, a semiconductor pillar extending in a stacking direction of the stacked body, and a charge storage film provided between the electrode films and the semiconductor pillar and extending linearly in the stacking direction of the stacked body. A stacking-direction width of an edge portion of the electrode films on side of the semiconductor pillar is shorter than a stacking-direction width of the electrode films other than the edge portion of the electrode films.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.