Abstract: An electronic device may have transparent housing structures such as walls formed of glass or sapphire. Housing structures such as transparent housing structures may have a colored coating. The colored coating may include an absorptive layer and a metal layer. The coating may exhibit a color that can be adjusted by adjusting the thickness of the thin absorptive layer. A colored layer such as a layer of colored polymer may be incorporated into the colored coating to further adjust the color of the coating. The colored coating may be formed on an inner or outer housing structure surface. The surface may have a texture to provide the coating with a matte appearance. When formed on an outer surface, a diamond-like carbon layer may protect the colored coating. When formed on an inner surface, a passivation layer may be used to prevent oxidation of the metal layer.

Abstract: An electronic device may have transparent housing structures such as walls formed of glass or sapphire. Housing structures such as transparent housing structures may have a colored coating. The colored coating may include an absorptive layer and a metal layer. The coating may exhibit a color that can be adjusted by adjusting the thickness of the thin absorptive layer. A colored layer such as a layer of colored polymer may be incorporated into the colored coating to further adjust the color of the coating. The colored coating may be formed on an inner or outer housing structure surface. The surface may have a texture to provide the coating with a matte appearance. When formed on an outer surface, a diamond-like carbon layer may protect the colored coating. When formed on an inner surface, a passivation layer may be used to prevent oxidation of the metal layer.

Abstract: An electronic device may have transparent housing structures such as walls formed of glass or sapphire. Housing structures such as transparent housing structures may have a colored coating. The colored coating may include an absorptive layer and a metal layer. The coating may exhibit a color that can be adjusted by adjusting the thickness of the thin absorptive layer. A colored layer such as a layer of colored polymer may be incorporated into the colored coating to further adjust the color of the coating. The colored coating may be formed on an inner or outer housing structure surface. The surface may have a texture to provide the coating with a matte appearance. When formed on an outer surface, a diamond-like carbon layer may protect the colored coating. When formed on an inner surface, a passivation layer may be used to prevent oxidation of the metal layer.

Abstract: A display may have a thin-film transistor layer and color filter layer. The display may have an active area and an inactive border area. Light blocking structures in the inactive area may prevent stray backlight from a backlight light guide plate from leaking out of the display. The thin-film transistor layer may have a clear substrate, a patterned black masking layer on the clear substrate, a clear planarization layer on the black masking layer, and a layer of thin-film transistor circuitry on the clear planarization layer. The black masking layer may be formed from black photoimageable polyimide. The clear planarization layer may be formed from spin-on glass. The light blocking structures may include a first layer formed from a portion of the black masking layer and a second layer such as a layer of black tape on the underside of the color filter layer.

Abstract: A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. A first low-k dielectric layer may be formed on the passivation layer. Data line routing structures may be formed on the first low-k dielectric layer. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. The first and second low-k dielectric layers may be formed from material having substantially similar refractive indices to maximize backlight transmittance and may have appropriate thicknesses so as to minimize parasitic capacitive loading.

Abstract: A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. A first low-k dielectric layer may be formed on the passivation layer. Data line routing structures may be formed on the first low-k dielectric layer. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. The first and second low-k dielectric, layers may be formed from material having substantially similar refractive indices to maximize backlight transmittance and may have appropriate thicknesses so as to minimize parasitic capacitive loading.

Abstract: A display may have a thin-film transistor layer and color filter layer. The display may have an active area and an inactive border area. Light blocking structures in the inactive area may prevent stray backlight from a backlight light guide plate from leaking out of the display. The thin-film transistor layer may have a clear substrate, a patterned black masking layer on the clear substrate, a clear planarization layer on the black masking layer, and a layer of thin-film transistor circuitry on the clear planarization layer. The black masking layer may be formed from black photoimageable polyimide. The clear planarization layer may be formed from spin-on glass. The light blocking structures may include a first layer formed from a portion of the black masking layer and a second layer such as a layer of black tape on the underside of the color filter layer.

Abstract: Display ground plane structures may contain slits. Image pixel electrodes in the display may be arranged in rows and columns. Image pixels in the display may be controlled using gate lines that are associated with the rows and data lines that are associated with the columns. An electric field may be produced by each image pixel electrode that extends through a liquid crystal layer to an associated portion of the ground plane. The slits in the ground plane may have a slit width. Data lines may be located sufficiently below the ground plane and sufficiently out of alignment with the slits to minimize crosstalk from parasitic electric fields. A three-column inversion scheme may be used when driving data line signals into the display, so that pairs of pixels that straddle the slits are each driven with a common polarity. Gate line scanning patterns may be used that enhance display uniformity.

Abstract: Display ground plane structures may contain slits. Image pixel electrodes in the display may be arranged in rows and columns. Image pixels in the display may be controlled using gate lines that are associated with the rows and data lines that are associated with the columns. An electric field may be produced by each image pixel electrode that extends through a liquid crystal layer to an associated portion of the ground plane. The slits in the ground plane may have a slit width. Data lines may be located sufficiently below the ground plane and sufficiently out of alignment with the slits to minimize crosstalk from parasitic electric fields. A three-column inversion scheme may be used when driving data line signals into the display, so that pairs of pixels that straddle the slits are each driven with a common polarity. Gate line scanning patterns may be used that enhance display uniformity.

Abstract: Display ground plane structures may contain slits. Image pixel electrodes in the display may be arranged in rows and columns. Image pixels in the display may be controlled using gate lines that are associated with the rows and data lines that are associated with the columns. An electric field may be produced by each image pixel electrode that extends through a liquid crystal layer to an associated portion of the ground plane. The slits in the ground plane may have a slit width. Data lines may be located sufficiently below the ground plane and sufficiently out of alignment with the slits to minimize crosstalk from parasitic electric fields. A three-column inversion scheme may be used when driving data line signals into the display, so that pairs of pixels that straddle the slits are each driven with a common polarity. Gate line scanning patterns may be used that enhance display uniformity.

Abstract: There is provided a liquid crystal display device that includes a liquid crystal layer interposed between a first substrate and a second substrate and has on a first substrate side a common electrode and a pixel electrode for applying an electric field to the liquid crystal layer, the liquid crystal display device including: a plurality of scan lines and a plurality of signal lines; a drive element; a first insulating film; a common electrode; a second insulating film; and a pixel electrode, wherein the common electrode covers the pixel area except a formation area of the contact hole on the first insulating film and at least one of the scan line and the signal line.

Abstract: After semiconductor wafers are loaded into a reaction vessel, and ruthenium (Ru) film or ruthenium oxide film is formed, the interior of the reaction vessel is efficiently cleaned without contaminating the wafers. The interior of the reaction vessel is heated to a temperature of above 850° C. while the pressure inside the reaction vessel is reduced to, e.g., 133 pa (1 Torr)-13.3 Kpa (100 Torr), and oxygen gas is fed into the reaction vessel at a flow rate of, e.g., above 1.5 Lm, whereby the ruthenium film or the ruthenium oxide film formed inside the reaction vessel is cleaned off. In place of oxygen gas, active oxygen, such as O3, O* and OH*, etc. may be used.

Abstract: There is provided a liquid crystal display device that includes a liquid crystal layer interposed between a first substrate and a second substrate and has on a first substrate side a common electrode and a pixel electrode for applying an electric field to the liquid crystal layer, the liquid crystal display device including: a plurality of scan lines and a plurality of signal lines; a drive element; a first insulating film; a common electrode; a second insulating film; and a pixel electrode, wherein the common electrode covers the pixel area except a formation area of the contact hole on the first insulating film and at least one of the scan line and the signal line.

Abstract: After semiconductor wafers are loaded into a reaction vessel, and ruthenium (Ru) film or ruthenium oxide film is formed, the interior of the reaction vessel is efficiently cleaned without contaminating the wafers. The interior of the reaction vessel is heated to a temperature of above 850° C. while the pressure inside the reaction vessel is reduced to, e.g., 133 pa (1 Torr)-13.3 Kpa (100 Torr), and oxygen gas is fed into the reaction vessel at a flow rate of, e.g., above 1.5 Lm, whereby the ruthenium film or the ruthenium oxide film formed inside the reaction vessel is cleaned off. In place of oxygen gas, active oxygen, such as O3, O* and OH*, etc. may be used.