Patents by Inventor Daisuke Oda

Daisuke Oda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146413
    Abstract: An object of the present invention is to provide a Brillouin gain spectrum distribution measuring method and apparatus capable of measuring a BGS, having a line width narrower than usual, in a distributed manner in the longitudinal direction of an optical fiber under test. This measuring apparatus prepares pump light in which a pulse is added to continuous light and probe light of continuous light in which a frequency is shifted from the pump light, makes the probe light incident on one end of the FUT and the pump light incident on the other end, and obtains a time waveform of a component amplified by the pump light pulse of a probe light intensity amplified by the pump light. This measuring apparatus changes an optical frequency difference between the pump light and the probe light, and obtains a time waveform for each optical frequency difference. This measuring apparatus obtains a BGS distribution of the FUT from these time waveforms.
    Type: Application
    Filed: January 26, 2021
    Publication date: May 2, 2024
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Tomokazu ODA, Daisuke IIDA, Atsushi NAKAMURA, Yusuke KOSHIKIYA, Nazuki HONDA
  • Patent number: 11951098
    Abstract: A method for suppressing obstruction of meibomian gland in a mammalian subject, the method comprising administering to the mammalian subject an eye drop comprising 0.01 to 0.5% (w/v) of sirolimus or a pharmaceutically acceptable salt thereof as a sole active ingredient, wherein the eye drop is administered to an eye of the mammalian subject 1 to 2 times per day.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: April 9, 2024
    Assignee: SANTEN PHARMACEUTICAL CO., LTD.
    Inventors: Hideki Miyake, Tomoko Oda, Daisuke Shii
  • Publication number: 20230131693
    Abstract: Provided is a motion sickness reduction system capable of providing a proper treatment tailored to a motion sickness state of each of two or more users. One aspect of the present disclosure is a motion sickness reduction system including a sensor that senses on-board states of the users aboard a vehicle, two or more communication terminals each assigned to the corresponding user, and an information processor that communicates with the communication terminals. The communication terminals each store motion sickness susceptibility data of the corresponding user to whom each communication terminal is assigned. The information processor performs a sickness level estimation process of estimating a sickness level of each user using the motion sickness susceptibility data and the corresponding on-board state sensed by the sensor, and a reduction treatment process of setting, for each user, a sickness reduction treatment based on the sickness level estimated.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 27, 2023
    Applicant: TOYOTA BOSHOKU KABUSHIKI KAISHA
    Inventors: Daisuke ODA, Akihiro KANOMUNE
  • Patent number: 11194369
    Abstract: The present invention is aiming at providing a communication apparatus that is lower in power consumption and that can detect a change in surrounding environment and send out information indicating the detection result, and a method to detect a change in surrounding environment. A communication apparatus of the present invention includes: a member containing a functional dye material that changes an optical property thereof in accordance with a change in surrounding environment and that maintains a post-change optical property; an optical sensor having a light-receiving portion and disposed such that the light-receiving portion receives light that has passed through the member, the optical sensor detecting a luminance of light that is received by the light-receiving portion; and a communication control unit that transmits information indicating the luminance detected by the optical sensor.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 7, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Daisuke Oda
  • Patent number: 11188802
    Abstract: An IC tag in which precision reduction is suppressed and which is compact and manufactured easily, and a manufacturing method of IC tag are provided. The IC tag has: antennas disposed on one surface of a substrate; a capacitor which includes a dielectric and first and second electrodes disposed on one surface of the substrate, and in which an electrostatic capacitance changes irreversibly corresponding to changes in ambient environment; and an IC chip which detects the electrostatic capacitance of the capacitor via a pair of external terminals to which the first and second electrodes are respectively connected, and wirelessly transmits information based on a detection result via the antennas.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 30, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Daisuke Oda
  • Publication number: 20210102966
    Abstract: A moving mechanism and a spray mechanism are controlled to spray a reagent from a nozzle to a sample plate while relatively moving the sample plate and the nozzle. The reagent is applied to an entire application area by moving a spray spot of the reagent sprayed from the nozzle, on the sample plate from a start point to an end point. At this time, the spray spot is moved in a sample placement area after a spray amount of the reagent from the nozzle and a moving speed of the spray spot become constant.
    Type: Application
    Filed: September 11, 2020
    Publication date: April 8, 2021
    Applicant: SHIMADZU CORPORATION
    Inventors: Mio TSUKAHARA, Kenta TERASHIMA, Yoshitake YAMAMOTO, Daisuke ODA
  • Publication number: 20200210801
    Abstract: An IC tag in which precision reduction is suppressed and which is compact and manufactured easily, and a manufacturing method of IC tag are provided. The IC tag has: antennas disposed on one surface of a substrate; a capacitor which includes a dielectric and first and second electrodes disposed on one surface of the substrate, and in which an electrostatic capacitance changes irreversibly corresponding to changes in ambient environment; and an IC chip which detects the electrostatic capacitance of the capacitor via a pair of external terminals to which the first and second electrodes are respectively connected, and wirelessly transmits information based on a detection result via the antennas.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 2, 2020
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Daisuke Oda
  • Publication number: 20190302018
    Abstract: The present invention is aiming at providing a communication apparatus that is lower in power consumption and that can detect a change in surrounding environment and send out information indicating the detection result, and a method to detect a change in surrounding environment. A communication apparatus of the present invention includes: a member containing a functional dye material that changes an optical property thereof in accordance with a change in surrounding environment and that maintains a post-change optical property; an optical sensor having a light-receiving portion and disposed such that the light-receiving portion receives light that has passed through the member, the optical sensor detecting a luminance of light that is received by the light-receiving portion; and a communication control unit that transmits information indicating the luminance detected by the optical sensor.
    Type: Application
    Filed: March 19, 2019
    Publication date: October 3, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Daisuke ODA
  • Patent number: 10417545
    Abstract: A detection device includes a first antenna configured to receive a first radio wave transmitted from an external device, a second antenna configured to receive the first radio wave transmitted from the external device, and transmit a second radio wave to the external device; and a chip configured to obtain a comparison result between a first electromotive force generated by the first radio wave received by the first antenna and a second electromotive force generated by the first radio wave received by the second antenna, and to send the comparison result to the external device through the second radio waive. When the first antenna is disposed closer than the second antenna to a place where the existence of moisture is to be detected, a change of the first electromotive force is greater than a change of the second electromotive force in response to the existence of moisture.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: September 17, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Daisuke Oda
  • Publication number: 20180218249
    Abstract: A detection device includes a first antenna configured to receive a first radio wave transmitted from an external device, a second antenna configured to receive the first radio wave transmitted from the external device, and transmit a second radio wave to the external device; and a chip configured to obtain a comparison result between a first electromotive force generated by the first radio wave received by the first antenna and a second electromotive force generated by the first radio wave received by the second antenna, and to send the comparison result to the external device through the second radio waive. When the first antenna is disposed closer than the second antenna to a place where the existence of moisture is to be detected, a change of the first electromotive force is greater than a change of the second electromotive force in response to the existence of moisture.
    Type: Application
    Filed: January 25, 2018
    Publication date: August 2, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Daisuke ODA
  • Patent number: 8127201
    Abstract: A nonvolatile memory includes a memory cell array having multiple memory cells, a read-out circuit outputting data stored in the memory cell array asynchronously in response to an input address signal, a selection circuit outputting a selection signal for selecting a location of the memory cell to fail, an error making circuit receiving a test mode signal, making the data outputted from the read-out circuit fail so that the failed data have an error, and outputting the failed data in response to the selection signal when the test mode signal is activated, and outputting the data outputted from the read-out circuit when the test mode signal is not activated, a data latch circuit latching either the failed data or the data outputted from the read-out circuit and outputting the latched data, and an error correcting circuit detecting the error in the latched data, correcting the error, and outputting the corrected signal.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: February 28, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Daisuke Oda, Bunsho Kuramori
  • Patent number: 7656322
    Abstract: A semiconductor memory device configured such that the time required for its access test can be reduced comprising a memory cell array, a row decoder, a column decoder, an error correction circuit, and an output circuit. The error correction circuit performs error correction on a code word read through the bit lines selected by the column decoder from ones of memory cells located at places at which the word line selected by the row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating the error position and corrects the information bit in the detected error position to generate error corrected data. The output circuit relays to the outside the error corrected data when a normal operation mode has been designated and the error detection data when a test operation mode has been designated.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: February 2, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Daisuke Oda
  • Publication number: 20090073009
    Abstract: A semiconductor memory device configured such that the time required for its access test can be reduced comprising a memory cell array, a row decoder, a column decoder, an error correction circuit, and an output circuit. The error correction circuit performs error correction on a code word read through the bit lines selected by the column decoder from ones of memory cells located at places at which the word line selected by the row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating the error position and corrects the information bit in the detected error position to generate error corrected data. The output circuit relays to the outside the error corrected data when a normal operation mode has been designated and the error detection data when a test operation mode has been designated.
    Type: Application
    Filed: July 18, 2008
    Publication date: March 19, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Daisuke Oda
  • Publication number: 20090077337
    Abstract: The present invention provides a data reading method suitable for use in a semiconductor memory device equipped with a plurality of semiconductor memory chips, which is capable of suppressing an increase in layout area as compared with a required storage capacity, and a semiconductor memory device. Two memory chips are sequentially selected in the way of combinations different from each other from within a plurality of memory chips each having a first storage area and a second storage area. Data are simultaneously read from the first storage area of one of the selected two memory chips and the second storage area of the other thereof.
    Type: Application
    Filed: July 18, 2008
    Publication date: March 19, 2009
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Daisuke ODA
  • Patent number: 7499328
    Abstract: A memory cell array circuit of a non-volatile memory selects the drain electrodes of the memory cells, interconnected to word lines and bit lines, by two drain selectors, adapted for selecting the drain electrodes in two selection routes, so that the memory cell array circuit will select the drain electrodes in four selection routes. In writing in the memory cells, the drain electrodes of the memory cells are selected at a rate of one out of four drain electrodes and the voltage CDV is applied to the so selected drain electrode. This decreases the potential difference between the drain and source electrodes of the non-selected memory cells to prevent the erroneous writing in the non-selected memory cells. A method for writing in the memory is also provided.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: March 3, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Daisuke Oda
  • Publication number: 20080184082
    Abstract: A nonvolatile memory includes a memory cell array having a plurality of memory cells, a read-out circuit outputting data stored in the memory cell array asynchronously in response to an input address signal, a selection circuit outputting an selection signal for selecting a location of the memory cell to be failed, an error making circuit receiving a test mode signal, making the data outputted from the read-out circuit fail and outputting the failed data in response to the selection signal when the test mode signal is activated, and outputting the data outputted from the read-out circuit when the test mode signal is not activated, a data latch circuit latching either the failed data or the data outputted from the read-out circuit and outputting the latched data, and an error correcting circuit detecting the error in the latched data, correcting the error, and outputting the corrected signal.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 31, 2008
    Inventors: Daisuke ODA, Bunsho Kuramori
  • Publication number: 20070133302
    Abstract: A memory cell array circuit of a non-volatile memory selects the drain electrodes of the memory cells, interconnected to word lines and bit lines, by two drain selectors, adapted for selecting the drain electrodes in two selection routes, so that the memory cell array circuit will select the drain electrodes in four selection routes. In writing in the memory cells, the drain electrodes of the memory cells are selected at a rate of one out of four drain electrodes and the voltage CDV is applied to the so selected drain electrode. This decreases the potential difference between the drain and source electrodes of the non-selected memory cells to prevent the erroneous writing in the non-selected memory cells. A method for writing in the memory is also provided.
    Type: Application
    Filed: November 3, 2006
    Publication date: June 14, 2007
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Daisuke Oda