Patents by Inventor Daisuke Oishi

Daisuke Oishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250069614
    Abstract: A signal filtering device includes: a separation unit that separates a predetermined number of possibility signals from a mixed signal as possibilities of a target signal; an encoding unit that encodes related information of the target signal into a first feature vector and encodes the predetermined number of possibility signals into the predetermined number of second feature vectors; and a selection unit that derives a similarity between the first feature vector and the second feature vector for each of the possibility signals, and selects a possibility signal of the possibility signals having the highest similarity as the target signal from the predetermined number of possibility signals. The selection unit may derive an inner product of the first feature vector and the second feature vector as the similarity. The predetermined number of possibility signals may be voice signals associated with the predetermined number of sound sources.
    Type: Application
    Filed: December 27, 2021
    Publication date: February 27, 2025
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yasunori OISHI, Marc DELCROIX, Tsubasa OCHIAI, Shoko ARAKI, Daiki TAKEUCHI, Daisuke NIIZUMI, Akisato KIMURA, Noboru HARADA, Kunio KASHINO
  • Publication number: 20060197619
    Abstract: [Problem] To provide a method of manufacturing a piezoelectric oscillator capable of preventing poor DLD characteristics that tend to occur in the piezoelectric oscillator including a piezoelectric resonator element and an IC chip that are sealed in the same package. [Means to Solve the Problem] A step of chemically polishing a surface without an integrated circuit of a silicon wafer 31 (step S2), a step of cleaning the silicon wafer 31 (step S3), a step of cutting the silicon wafer 31 into individual pieces of IC chip 6 (step S5), a step of bonding the IC chip 6 facing downwards in a recessed section of an insulating container, a step of mounting a piezoelectric resonator element in the insulating container, and a step of sealing with metal cover are included.
    Type: Application
    Filed: January 11, 2006
    Publication date: September 7, 2006
    Applicant: EPSON TOYOCOM CORPORATION
    Inventors: Daisuke Oishi, Makoto Komai