Patents by Inventor Daisuke Okazawa

Daisuke Okazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962329
    Abstract: The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity. A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 16, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Tatsuya Sugioka, Toshihisa Hyakudai, Masayuki Unuma, Daisuke Okazawa, Aritoshi Kimura, Hiroshi Shiroshita
  • Publication number: 20230308210
    Abstract: The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity. There are provided: a calculation section dividing inputted data into N bits to calculate a first running disparity of a data string of the N bits; a determination section determining whether the data string of the N bits is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated at a time point before the first running disparity; and an addition section inverting or non-inverting the data string of the N bits based on a result of the determination by the determination section to add a flag indicating the result of the determination by the determination section for outputting. The technology is applicable to a device communicating in an SLVS-EC specification.
    Type: Application
    Filed: June 29, 2020
    Publication date: September 28, 2023
    Inventors: Tatsuya Sugioka, Toshihisa Hyakudai, Masayuki Unuma, Daisuke Okazawa, Aritoshi Kimura, Hiroshi Shiroshita
  • Publication number: 20230223953
    Abstract: Encoding devices, methods and programs that encode with high transmission efficiency by controlling a running disparity are disclosed. In one example, an encoding device includes a scrambling circuit that scrambles an input data string, a calculation circuit that calculates a first running disparity of the scrambled data string, a determination circuit that determines whether or not to invert the scrambled data string on the basis of a first running disparity calculated by the calculation circuit and a second running disparity calculated at a time point before the first running disparity, and an addition circuit that inverts or non-inverts the scrambled data string on the basis of a determination result by the determination circuit, adds a flag indicating the determination result, and outputs the data string. The technology can be applied to devices that perform SLVS-EC standard communication.
    Type: Application
    Filed: June 16, 2021
    Publication date: July 13, 2023
    Inventors: Masayuki Unuma, Hiroshi Shiroshita, Daisuke Okazawa, Aritoshi Kimura
  • Publication number: 20220368353
    Abstract: The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity. A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.
    Type: Application
    Filed: June 30, 2020
    Publication date: November 17, 2022
    Inventors: Tatsuya Sugioka, Toshihisa Hyakudai, Masayuki Unuma, Daisuke Okazawa, Aritoshi Kimura, Hiroshi Shiroshita