Patents by Inventor Daisuke Shinoda

Daisuke Shinoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11970662
    Abstract: An electrochromic element including: a first electrode; a second electrode disposed to face the first electrode with a gap between the first electrode and the second electrode; a first electrochromic layer disposed on or above the first electrode, including conductor or semiconductor nano-structures and an electrochromic compound; and an electrolyte layer including an electrolyte, disposed between the first electrochromic layer and the second electrode, wherein the electrochromic compound is a compound represented by General Formula 1, and an anion of the electrolyte is a monovalent anion having oxidation potential higher than reduction potential of a dication of General Formula 1 by 3.1 V or greater, where X? is a monovalent anion having oxidation potential higher than reduction potential of the dication of General Formula 1 by 3.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: April 30, 2024
    Assignee: RICOH COMPANY, LTD.
    Inventors: Fuminari Kaneko, Daisuke Goto, Masato Shinoda, Ryo Kawamura, Naru Tanaka, Tohru Yashiro, Mamiko Inoue, Naoki Ura
  • Publication number: 20230352573
    Abstract: A semiconductor element includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first intermediate layer, a second intermediate layer, a source electrode, a drain electrode, and a gate electrode. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The band gaps of the first intermediate layer and the second intermediate layer that sandwich the second semiconductor layer are larger than the band gap of the second semiconductor layer.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 2, 2023
    Inventors: Hisao SATO, Koji OKUNO, Daisuke SHINODA, Toshiya UEMURA, Hironobu NARUI, Hiroji KAWAI, Shuichi YAGI
  • Patent number: 10644204
    Abstract: A method of manufacturing a light emitting element includes forming an n-type semiconductor layer that includes an n-type clad layer and AlxGa1-xN (0.1?x?1) as a main component, forming an n-side contact electrode that includes a laminate structure including a Ti layer and a Ru layer, the Ti layer being in contact with the n-type semiconductor layer, and forming an ohmic contact of the n-type semiconductor layer and the Ti layer by a heat treatment.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 5, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yasuhiro Takenaka, Yoshiki Saito, Shinichi Matsui, Daisuke Shinoda, Takashi Hodota, Hironao Shinohara
  • Patent number: 10461214
    Abstract: To provide a method for producing a Group III nitride semiconductor light-emitting device using a substrate containing Al such as AlN substrate while suppressing polarity inversion. The production method comprising an oxide film formation step, a first Group III nitride layer formation step, a first semiconductor layer formation step, a light-emitting layer formation step, and a second semiconductor layer formation step. In the production method, an AlN substrate or AlGaN substrate is employed. In the oxide film formation step, an oxide film containing Al atoms, N atoms, and O atoms is formed. In the first Group III nitride layer formation step, an AlN layer or AlGaN layer is formed as the first Group III nitride layer under the condition that the substrate temperature 1200° C. to 1450° C.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 29, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yoshiki Saito, Daisuke Shinoda
  • Patent number: 10128411
    Abstract: A light-emitting element includes an n-type semiconductor layer mainly including AlxGa1?XN (0.5?x?1), a p-type semiconductor layer, a light-emitting layer sandwiched between the n-type semiconductor layer and the p-type semiconductor layer, an n-electrode connected to the n-type semiconductor layer, and a plurality of p-electrodes that are connected to the p-type semiconductor layer and are arranged in a dot pattern. An area of the n-electrode is not less than 25% and not more than 50% of a chip area.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: November 13, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yasuhiro Takenaka, Yoshiki Saito, Shinichi Matsui, Daisuke Shinoda, Hisayuki Miki, Hironao Shinohara
  • Publication number: 20180182916
    Abstract: To provide a Group III nitride semiconductor light-emitting device in which a semiconductor layer is grown using a substrate containing Al such as AlN substrate while suppressing polarity inversion, and a production method therefor. The light-emitting device includes a substrate, a first oxide film formed in contact with the substrate, a first Group III nitride layer formed in contact with the first oxide film, a second oxide film formed in contact with the first Group III nitride layer, and an n-type contact layer on the second oxide film. The substrate is an AlN substrate or AlGaN substrate. The first oxide film contains Al atoms, N atoms, and O atoms. The first Group III nitride layer comprises AlN or AlGaN. The second oxide film contains Al atoms, N atoms, and O atoms.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 28, 2018
    Inventors: Yoshiki Saito, Daisuke Shinoda
  • Publication number: 20180182915
    Abstract: To provide a method for producing a Group III nitride semiconductor light-emitting device using a substrate containing Al such as AlN substrate while suppressing polarity inversion. The production method comprising an oxide film formation step, a first Group III nitride layer formation step, a first semiconductor layer formation step, a light-emitting layer formation step, and a second semiconductor layer formation step. In the production method, an AlN substrate or AlGaN substrate is employed. In the oxide film formation step, an oxide film containing Al atoms, N atoms, and O atoms is formed. In the first Group III nitride layer formation step, an AlN layer or AlGaN layer is formed as the first Group III nitride layer under the condition that the substrate temperature 1200° C. to 1450° C.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 28, 2018
    Inventors: Yoshiki Saito, Daisuke Shinoda
  • Publication number: 20180083164
    Abstract: A light-emitting element includes an n-type semiconductor layer mainly including AlxGa1-XN (0.5?x?1), a p-type semiconductor layer, a light-emitting layer sandwiched between the n-type semiconductor layer and the p-type semiconductor layer, an n-electrode connected to the n-type semiconductor layer, and a plurality of p-electrodes that are connected to the p-type semiconductor layer and are arranged in a dot pattern. An area of the n-electrode is not less than 25% and not more than 50% of a chip area.
    Type: Application
    Filed: July 6, 2017
    Publication date: March 22, 2018
    Inventors: Yasuhiro TAKENAKA, Yoshiki SAITO, Shinichi MATSUI, Daisuke SHINODA, Hisayuki MIKI, Hironao SHINOHARA
  • Publication number: 20180083166
    Abstract: A method of manufacturing a light emitting element includes forming an n-type semiconductor layer that includes an n-type clad layer and AlxGa1-xN (0.1?x?1) as a main component, forming an n-side contact electrode that includes a laminate structure including a Ti layer and a Ru layer, the Ti layer being in contact with the n-type semiconductor layer, and forming an ohmic contact of the n-type semiconductor layer and the Ti layer by a heat treatment.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 22, 2018
    Inventors: Yasuhiro TAKENAKA, Yoshiki Saito, Shinichi Matsui, Daisuke Shinoda, Takashi Hodota, Hironao Shinohara
  • Publication number: 20180083163
    Abstract: A method of manufacturing a light-emitting device includes forming by sputtering a nucleation layer mainly including AlN on a surface of a patterned substrate including a concave-convex pattern, after forming the nucleation layer, performing a heat treatment at a temperature of not less than 1150° C., after the heat treatment, forming an AlGaN underlayer on the surface of the patterned substrate with the nucleation layer formed thereon, the AlGaN underlayer mainly including AlxGa1?xN (0.04?x?1) and a flat surface, and epitaxially growing a group III nitride semiconductor on the AlGaN underlayer so as to form a light-emitting function portion including a light-emitting layer.
    Type: Application
    Filed: July 24, 2017
    Publication date: March 22, 2018
    Inventors: Yoshiki SAITO, Daisuke SHINODA, Akira TANEICHI, Hisayuki MIKI, Kazutaka YOSHIMURA
  • Patent number: 8765509
    Abstract: A method for producing a Group III nitride semiconductor light-emitting device includes an n-type layer, a light-emitting layer, and a p-type layer, each of the layers being formed of Group III nitride semiconductor, being sequentially deposited via a buffer layer on a textured sapphire substrate. A buried layer is formed of Group III nitride semiconductor on the buffer layer, at a temperature lower by 20° C. to 80° C. than the temperature of 1000° C. to 1200° C. when the n-type layer is deposited on the buried layer. The texture provided on the sapphire substrate may have a depth of 1 ?m to 2 ?m and a side surface inclined by 40° to 80°. A preventing layer may be formed of GaN at 600° C. to 1050° C. so as to cover the entire top surface of the buffer layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 1, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Daisuke Shinoda, Shugo Nitta, Yoshiki Saito
  • Publication number: 20120083063
    Abstract: A method for producing a Group III nitride semiconductor light-emitting device includes an n-type layer, a light-emitting layer, and a p-type layer, each of the layers being formed of Group III nitride semiconductor, being sequentially deposited via a buffer layer on a textured sapphire substrate. A buried layer is formed of Group III nitride semiconductor on the buffer layer, at a temperature lower by 20° C. to 80° C. than the temperature of 1000° C. to 1200° C. when the n-type layer is deposited on the buried layer. The texture provided on the sapphire substrate may have a depth of 1 ?m to 2 ?m and a side surface inclined by 40° to 80°. A preventing layer may be formed of GaN at 600° C. to 1050° C. so as to cover the entire top surface of the buffer layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: April 5, 2012
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Daisuke Shinoda, Shugo Nitta, Yoshiki Saito
  • Patent number: 7524741
    Abstract: A method of forming a low temperature-grown buffer layer having the steps of: placing a Ga2O3 substrate in a MOCVD apparatus; providing a H2 atmosphere in the MOCVD apparatus and setting a buffer layer growth condition having an atmosphere temperature of 350° C. to 550° C.; and supplying a source gas having two or more of TMG, TMA and NH3 onto the Ga2O3 substrate in the buffer layer growth condition to form the low temperature-grown buffer layer on the Ga2O3 substrate.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 28, 2009
    Assignees: Toyoda Gosei Co., Ltd., Koha Co., Ltd.
    Inventors: Yasuhisa Ushida, Daisuke Shinoda, Daisuke Yamazaki, Koji Hirata, Yuhei Ikemoto, Naoki Shibata, Kazuo Aoki, Encarnacion Antonia Garcia Villora, Kiyoshi Shimamura
  • Patent number: 7397220
    Abstract: Metal cell tanks including secondary cells respectively are connected to one another by connection members. For example, a connection member has: an insulation portion interposed between adjacent cell tanks for keeping the cell tanks electrically insulated from each other; an one-end holding portion extending from one end of the insulation portion for holding one end portion of one of the adjacent cell tanks; and an opposite-end holding portion extending from the other end of the insulation portion for holding the other end portion of the other of the adjacent cell tanks.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: July 8, 2008
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yasunori Uchida, Yasushi Ido, Isao Takada, Daisuke Shinoda, Katsuya Hadano
  • Publication number: 20060223287
    Abstract: A method of forming a low temperature-grown buffer layer having the steps of: placing a Ga2O3 substrate in a MOCVD apparatus; providing a H2 atmosphere in the MOCVD apparatus and setting a buffer layer growth condition having an atmosphere temperature of 350° C. to 550° C.; and supplying a source gas having two or more of TMG, TMA and NH3 onto the Ga2O3 substrate in the buffer layer growth condition to form the low temperature-grown buffer layer on the Ga2O3 substrate.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 5, 2006
    Applicants: Toyoda Gosei Co., Ltd, KOHA Co., Ltd.
    Inventors: Yasuhisa Ushida, Daisuke Shinoda, Daisuke Yamazaki, Koji Hirata, Yuhei Ikemoto, Naoki Shibata, Kazuo Aoki, Encarnacion Garcia Villora, Kiyoshi Shimamura
  • Publication number: 20050212477
    Abstract: Metal cell tanks including secondary cells respectively are connected to one another by connection members. For example, a connection member has: an insulation portion interposed between adjacent cell tanks for keeping the cell tanks electrically insulated from each other; an one-end holding portion extending from one end of the insulation portion for holding one end portion of one of the adjacent cell tanks; and an opposite-end holding portion extending from the other end of the insulation portion for holding the other end portion of the other of the adjacent cell tanks.
    Type: Application
    Filed: March 29, 2005
    Publication date: September 29, 2005
    Inventors: Yasunori Uchida, Yasushi Ido, Isao Takada, Daisuke Shinoda, Katsuya Hadano