Abstract: A memory controller that is formed to be able to issue a first write command for writing data of a predetermined length into a DRAM and a second write command for writing data which is less than the predetermined length in the DRAM is provided. The memory controller comprises a deciding unit configured to decide an issuance order of a request stored in the storage unit. In a period from the issuance of a preceding DRAM command until a second write command targeting the same bank as the preceding DRAM command is issued, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued, the deciding unit will decide the issuance order so that the other DRAM command that can be issued will be issued before the second write command.

Abstract: A memory controller includes a storing unit configured to store one or more read or write access requests, a first generation unit configured to generate a read command or write command based on the access requests stored in the storing unit, a second generation unit configured to generate a page control command based on the access requests stored in the storing unit, and an issuance unit configured to, in a case where the read command or the write command generated by the first generation unit and the page control command generated by the second generation unit conflict with each other, then based on access requests in which pages are already opened among the access requests stored in the storing unit, issue either of the read command or the write command generated by the first generation unit and the page control command generated by the second generation unit to a memory.

Abstract: To increase convenience of an operation performed from a vehicle stop state until ACC is started or resumed, provided is a driving assistance device for a vehicle, including: a control unit (11) configured to execute travel control of at least one of constant-speed travel control or follow-up travel control, and to stop the travel control during stop of the own vehicle (100); a detection unit (43, 13) configured to detect release of a brake pedal by an occupant of the own vehicle (100); and a reception unit (60, 13) configured to receive an assistance request from the occupant. The control unit (11) is configured to execute one of start or resumption of the travel control when the detection unit (43, 13) detects the release of the brake pedal and the reception unit (60, 13) receives the assistance request during the stop of the own vehicle (100).

Abstract: A memory control circuit includes an access storage unit configured to store access requests for a memory, a status management unit configured to, based on the access requests stored in the access storage unit, perform priority access type switching between two access types obtained by classifying the access requests, and an access selection unit configured to select and execute an access request stored in the storage unit. The access selection unit performs, if the priority access type switching is in progress and there is time for executing an access request of a priority access type before the priority access type switching, selecting the access request of the priority access type before the priority access type switching, and if the priority access type switching is not in progress, selecting an access request of the priority access type.

Abstract: A memory controller for accessing a memory, comprises a holding circuit which holds a plurality of read or write access requests from a bus master, a read/write control circuit which selects one of the access requests in the holding circuit and issues a read command or a write command; and an active control circuit which selects the access request held in the holding circuit and issues an active command, wherein the active control circuit includes a generation circuit that generates number of activated read commands and number of activated write commands, and a selection circuit that, when the number of activated read commands is not less a threshold, issues the active command of an read access, and when the number of activated write commands is not less than the threshold, issues the active command of a write access.

Abstract: A plasma processing apparatus, to which process control such as APC is applied, includes: a processing chamber in which plasma processing is performed on a sample; and a plasma processing control device which performs control to optimize a condition for plasma processing which recovers the status inside a processing chamber, in which plasma processing is performed, based on a waiting time from the time when plasma processing for a second lot, which is a lot immediately before a first lot, is completed to the time when plasma processing for the first lot is started, and the content of plasma processing for the second lot.

Abstract: In a memory controller, at least one of a plurality of refresh methods varying in refresh target area of a dynamic random access memory (DRAM) is a refresh method of refreshing an entire area of the DRAM, and a specific event that disables access to the entire area of the DRAM occurs in a cycle longer than a refresh execution cycle using the refresh method of refreshing the entire area of the DRAM. The memory controller includes a selection unit configured to select one refresh method from among the plurality of refresh methods, depending on whether the specific event that disables the access to the entire area of the DRAM is to occur in a refresh execution period.

Abstract: An imaging device includes an image sensing unit configured to generate image data by sensing incident light received from a scene, a line buffer configured to store image data received from the image sensing unit, an optical distortion corrector (ODC) configured to perform lens distortion correction for output pixel coordinates based on input pixel coordinates of the image data stored in the line buffer, and a read speed controller configured to control a read speed at which the image data is read from the line buffer according to the output pixel coordinates.

Abstract: In time-series data indicating light emission of plasma when plasma processing is carried out on a sample by generating the plasma, an analysis apparatus creates combinations of a plurality of light emission wavelengths of elements and a plurality of time intervals within a plasma processing interval and calculates, for each of the combinations of the wavelengths and the time intervals, a correlation between an average value of light emission intensity and the number of times the plasma processing is carried out on the samples for each of the combinations of the wavelengths and the time intervals that have been created. Thereafter, the data analysis apparatus selects, as a combination of the wavelength and the time interval used to observe or control the plasma processing, a combination of a wavelength of light emitting from a specific element and a specific time interval having a maximum correlation.

Abstract: A memory controller configured to control a dynamic random access memory (DRAM) includes a first control circuit and a second control circuit. The first control circuit is configured to store a request received by the memory controller in a first storage circuit, and select a request from all requests stored in the first storage circuit. The second control circuit is configured to store the request selected by the first control circuit in a second storage circuit, reorder requests stored in the second storage circuit, generate a DRAM command, and issue the DRAM command to the DRAM. The first control circuit is configured to select the request based on target banks and target pages of the requests stored in the second storage circuit, and a state of a bank or page of the DRAM.

Abstract: In a control circuit, a request storage unit including a plurality of entries for storing an access request, to which a priority and attribute information are applied, stores the received access request, a priority update unit updates the priority of the access request based on the priority and the attribute information of the access request stored in the request storage unit, and a request selection unit selects and transmits the access request stored in the request storage unit based on the updated priority.

Abstract: A memory control circuit includes an access storage unit configured to store access requests for a memory, a status management unit configured to, based on the access requests stored in the access storage unit, perform priority access type switching between two access types obtained by classifying the access requests, and an access selection unit configured to select and execute an access request stored in the storage unit. The access selection unit performs, if the priority access type switching is in progress and there is time for executing an access request of a priority access type before the priority access type switching, selecting the access request of the priority access type before the priority access type switching, and if the priority access type switching is not in progress, selecting an access request of the priority access type.

Abstract: There is provided a method of analyzing data obtained from an etching apparatus for micromachining a wafer using plasma. This method includes the following steps: acquiring the plasma light-emission data indicating light-emission intensities at a plurality of different wavelengths and times, the plasma light-emission data being measured under a plurality of different etching processing conditions, and being obtained at the time of the etching processing, evaluating the relationship between changes in the etching processing conditions and changes in the light-emission intensities at the plurality of different wavelengths and times with respect to the wavelengths and times of the plasma light-emission data, and identifying the wavelength and the time of the plasma light-emission data based on the evaluation result, the wavelength and the time being to be used for the adjustment of the etching processing condition.

Abstract: A memory controller is able to issue a first write command for writing data of a predetermined length into a DRAM and a second write command for writing data which is less than the predetermined length in the DRAM. The memory controller includes a deciding unit configured to decide an issuance order of one or more requests stored in a storage unit. In a period from the issuance of a preceding DRAM command until a second write command targeting the same bank as the preceding DRAM command is issued, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued, the deciding unit will decide the issuance order so that the other DRAM command that can be issued will be issued before the second write command.

Abstract: There is provided a method of analyzing data obtained from an etching apparatus for micromachining a wafer using plasma. This method includes the following steps: acquiring the plasma light-emission data indicating light-emission intensities at a plurality of different wavelengths and times, the plasma light-emission data being measured under a plurality of different etching processing conditions, and being obtained at the time of the etching processing, evaluating the relationship between changes in the etching processing conditions and changes in the light-emission intensities at the plurality of different wavelengths and times with respect to the wavelengths and times of the plasma light-emission data, and identifying the wavelength and the time of the plasma light-emission data based on the evaluation result, the wavelength and the time being to be used for the adjustment of the etching processing condition.

Abstract: A memory controller for accessing a memory, comprises a holding circuit which holds a plurality of read or write access requests from a bus master, a read/write control circuit which selects one of the access requests in the holding circuit and issues a read command or a write command; and an active control circuit which selects the access request held in the holding circuit and issues an active command, wherein the active control circuit includes a generation circuit that generates number of activated read commands and number of activated write commands, and a selection circuit that, when the number of activated read commands is not less a threshold, issues the active command of an read access, and when the number of activated write commands is not less than the threshold, issues the active command of a write access.

Abstract: According to the present invention, a plasma processing apparatus includes an analysis unit that obtains wavelengths of the light correlated with a plasma processing result, selects, from the obtained wavelengths, a wavelength having a first factor that represents a deviation in an intensity distribution of the light and is larger than a first predetermined value, and predicts the plasma processing result using the selected wavelength, or an analysis unit that obtains values computed using each of light intensities of a plurality of wavelengths and correlated with the plasma processing result, selects, from the obtained values, a value having a second factor that represents a deviation in a distribution of the obtained values and is larger than a second predetermined value, and predicts the plasma processing result using the selected value.

Abstract: A memory controller that is formed to be able to issue a first write command for writing data of a predetermined length into a DRAM and a second write command for writing data which is less than the predetermined length in the DRAM is provided. The memory controller comprises a deciding unit configured to decide an issuance order of a request stored in the storage unit. In a period from the issuance of a preceding DRAM command until a second write command targeting the same bank as the preceding DRAM command is issued, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued, the deciding unit will decide the issuance order so that the other DRAM command that can be issued will be issued before the second write command.

Abstract: A bus system comprises a master, a first slave, a second slave, and a bus. The master is configured to be able to issue a second request to the second slave after issuing a first request to the first slave and before receiving a response to the first request. The bus comprises: a determination unit configured to, upon receiving the second request, determine whether to permit a transfer of the second request to the second slave; and a suspending unit configured to suspend the transfer of the second request to the second slave while it is determined by the determination unit that the transfer is not permitted. The determination unit determines whether or not the transfer is permitted based on a notification from the first slave regarding processing of the first request.

Abstract: A lens apparatus includes a detector configured to detect a camera shake, a correction unit configured to correct an image shake caused by the camera shake based on the detected camera shake, a driving device configured to move the correction unit, a holder holding the detector, and a fiber assembly via which the holder holds the detector.