Patents by Inventor Daisuke Taniguchi
Daisuke Taniguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220336219Abstract: A method for manufacturing a silicon carbide semiconductor device according to the technology disclosed in the present specification includes: forming a drift layer on an upper surface of a silicon carbide semiconductor substrate; forming a hard mask on the upper surface of the drift layer by anisotropic etching; and forming a first ion-implanted region in a surface layer of the drift layer by implanting ions into the drift layer in a state in which the hard mask is formed, in which the hard mask includes a sidewall perpendicular to the upper surface of the drift layer.Type: ApplicationFiled: February 1, 2022Publication date: October 20, 2022Applicant: Mitsubishi Electric CorporationInventors: Junya MIWA, Toshikazu TANIOKA, Daisuke TANIGUCHI
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Publication number: 20220239914Abstract: The present technology relates to an information processing device, an imaging device, an information processing method, and a program capable of generating an appropriate digital signal having high quantization precision from a digital signal having low quantization precision. High-precision component information is extracted from an unprocessed signal that is a digital signal not subjected to predetermined signal processing and having first quantization precision, and a reproduction signal in which quantization precision of a processed signal obtained by performing the predetermined signal processing on the unprocessed signal is reproduced to the first quantization precision on the basis of the high-precision component information is generated. The present technology is applicable to, for example, an imaging device.Type: ApplicationFiled: June 8, 2020Publication date: July 28, 2022Applicant: Sony Group CorporationInventor: Daisuke TANIGUCHI
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Patent number: 10355122Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).Type: GrantFiled: June 30, 2017Date of Patent: July 16, 2019Assignee: Renesas Electronics CorporationInventors: Yuya Abiko, Satoshi Eguchi, Shigeaki Saito, Daisuke Taniguchi, Natsuo Yamaguchi
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Publication number: 20180076313Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).Type: ApplicationFiled: June 30, 2017Publication date: March 15, 2018Inventors: Yuya ABIKO, Satoshi EGUCHI, Shigeaki SAITO, Daisuke TANIGUCHI, Natsuo YAMAGUCHI
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Patent number: 9745404Abstract: Provided is a resin molded article for an automobile interior material, the resin molded article achieving both resin strength permitting formation of a thin film, and crease resistance. This molded article is to be used in an automobile interior material, the resin molded article being obtained by slush-molding a powdered thermoplastic urethane urea resin composition (P) that satisfies (1)-(5) below, said resin composition (P) containing an additive and a thermoplastic urethane urea resin (U) obtained by reacting a high-molecular diol (a), a linear alkane diol (b), a monool (c), a diamine (d), and an organic diisocyanate (e): (1) (a) contains a specific polyester diol; (2) the weight of (b) is within a specific range relative to the total weight of (a)-(e); (3) the tensile strength of a film comprising (P) is 8.0 MPa or higher; (4) the storage modulus of (P) at 130° C. is 0.1-5.0 MPa; (5) the ratio of the storage modulus of (P) at 50° C. to the storage modulus at 23° C.Type: GrantFiled: April 23, 2015Date of Patent: August 29, 2017Assignees: SANYO CHEMICAL INDUSTRIES, LTD., TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kenta Nose, Koichi Saito, Osami Yamada, Hiroyuki Ishii, Daisuke Taniguchi
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Publication number: 20170044300Abstract: Provided is a resin molded article for an automobile interior material, the resin molded article achieving both resin strength permitting formation of a thin film, and crease resistance. This molded article is to be used in an automobile interior material, the resin molded article being obtained by slush-molding a powdered thermoplastic urethane urea resin composition (P) that satisfies (1)-(5) below, said resin composition (P) containing an additive and a thermoplastic urethane urea resin (U) obtained by reacting a high-molecular diol (a), a linear alkane diol (b), a monool (c), a diamine (d), and an organic diisocyanate (e): (1) (a) contains a specific polyester diol; (2) the weight of (b) is within a specific range relative to the total weight of (a)-(e); (3) the tensile strength of a film comprising (P) is 8.0 MPa or higher; (4) the storage modulus of (P) at 130° C. is 0.1-5.0 MPa; (5) the ratio of the storage modulus of (P) at 50° C. to the storage modulus at 23° C.Type: ApplicationFiled: April 23, 2015Publication date: February 16, 2017Applicants: SANYO CHEMICAL INDUSTRIES, LTD., TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kenta NOSE, Koichi SAITO, Osami YAMADA, Hiroyuki ISHII, Daisuke TANIGUCHI
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Publication number: 20160318285Abstract: There is provided a vehicle-interior material, and in particular an instrument panel, which is thin, and which imparts a pleasant tactile sensation. In this integrated-urethane foam molded vehicle-interior material, a urethane foam layer is integrally molded between a resin skin material and a base material. The thickness of the urethane foam layer is 2.5-6.0 mm. The urethane foam layer is a foam body formed from a mixed solution comprising: a polyol mixture (P) which includes a polyol (resin) (A), a water-containing foaming agent (C), and a catalyst (D); and a polyisocyanate component (B). The foaming agent (C) content is 1.5-2.5 wt % when the total weight of (A) is used as a reference. The thickness of the resin skin material is 0.6-1.0 mm. The surface of the skin material is displaced at least 0.40 mm by a load of 10N, and is displaced 1.5-2.5 mm by a load of 40N.Type: ApplicationFiled: December 16, 2014Publication date: November 3, 2016Applicants: SANYO CHEMICAL INDUSTRIES, LTD., TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shunsuke Kinoshita, Hiroki Hara, Yoichi Takagi, Daisuke Taniguchi
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Publication number: 20160079079Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.Type: ApplicationFiled: November 24, 2015Publication date: March 17, 2016Inventors: Satoshi EGUCHI, Daisuke TANIGUCHI
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Patent number: 9246627Abstract: A joint-optimization method addresses the generalized routing and wavelength assignment problem with variable number of combined 1+1 dedicated and shared connections. The inventive method enables a solution in time that is polynomial of the input size. Thus, the time complexity of the joint-optimization method is significantly less than that of existing methods.Type: GrantFiled: August 17, 2012Date of Patent: January 26, 2016Assignee: NEC Laboratories America, Inc.Inventors: Ankitkumar N. Patel, Philip Nan Ji, Yoshiaki Aono, Daisuke Taniguchi
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Patent number: 9240464Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.Type: GrantFiled: January 14, 2014Date of Patent: January 19, 2016Assignee: Renesas Electronics CorporationInventors: Satoshi Eguchi, Daisuke Taniguchi
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Patent number: 9054829Abstract: A spectrum-aware rate selection includes finding a set of channels based on spectrum availability information such that the total required spectrum for a requested data rate of a traffic demand is minimized.Type: GrantFiled: July 11, 2013Date of Patent: June 9, 2015Assignee: NEC Laboratories America, Inc.Inventors: Ankitkumar Patel, Philip Ji, Daisuke Taniguchi, Yoshiaki Aono
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Patent number: 8977123Abstract: The inventive 2-step-optimization procedure that addresses the generalized routing and wavelength assignment problem with variable number of combined 1+1 dedicated and shared connections for the first time. The proposed procedure results a solution in time that is polynomial of the input size. Thus, the time complexity of the 2-step-optimization procedure is significantly less than that of existing methods.Type: GrantFiled: August 17, 2012Date of Patent: March 10, 2015Assignee: NEC Laboratories America, Inc.Inventors: Ankitkumar N. Patel, Philip Nan Ji, Yoshiaki Aono, Daisuke Taniguchi
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Publication number: 20140206162Abstract: A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.Type: ApplicationFiled: January 14, 2014Publication date: July 24, 2014Applicant: Renesas Electronics CorporationInventors: Satoshi EGUCHI, Daisuke TANIGUCHI
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Patent number: 8760531Abstract: An image processing device includes: a first interpolation unit that performs interpolation using pixel information of pixels having a color same as a color of a pixel of attention and present around the pixel of attention; a second interpolation unit that interpolates color information lost in the pixel of attention using color information of the pixels around the pixel of attention; a combining unit that combines outputs of the first and second interpolation units; a first filter that includes a first filter frequency characteristic and detects a first image of a first region; a second filter that includes a second filter frequency characteristic and detects a second image of a second region; and a combination-ratio generating unit that generates a value for determining a combination ratio of the outputs of the first and second interpolation units in the combining unit.Type: GrantFiled: October 12, 2011Date of Patent: June 24, 2014Assignee: Sony CorporationInventors: Daisuke Taniguchi, Manabu Kawashima
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Publication number: 20140016939Abstract: A spectrum-aware rate selection includes finding a set of channels based on spectrum availability information such that the total required spectrum for a requested data rate of a traffic demand is minimized.Type: ApplicationFiled: July 11, 2013Publication date: January 16, 2014Applicant: NEC Laboratories America, Inc.Inventors: Ankitkumar Patel, Philip Ji, Daisuke Taniguchi, Yoshiaki Aono
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Patent number: 8542129Abstract: A parking aid system is disclosed. The parking aid system includes: a parking space borderline recognition section configured to recognize two borderlines of the parking space based on a captured image, which is captured by an imaging device mounted to the vehicle, the two borderlines respectively being two parts of the parking space boundary opposite to each other in a width direction of the parking space; a displacement calculation section configured to calculate displacement of the vehicle in the width direction with respect to the two borderlines based on positions of the two borderlines in the captured image and an imaging range of the imaging device; and a notifier configured to notify the displacement calculated by the displacement calculation section.Type: GrantFiled: June 8, 2010Date of Patent: September 24, 2013Assignee: DENSO CORPORATIONInventors: Daisuke Taniguchi, Ryusuke Kawano
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Publication number: 20130216225Abstract: The inventive 2-step-optimization procedure that addresses the generalized routing and wavelength assignment problem with variable number of combined 1+1 dedicated and shared connections for the first time. The proposed procedure results a solution in time that is polynomial of the input size. Thus, the time complexity of the 2-step-optimization procedure is significantly less than that of existing methods.Type: ApplicationFiled: August 17, 2012Publication date: August 22, 2013Applicant: NEC Laboratories America, Inc.Inventors: Ankitkumar N. Patel, Philip Nan Ji, Yoshiaki Aono, Daisuke Taniguchi
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Publication number: 20130216224Abstract: A joint-optimization method addresses the generalized routing and wavelength assignment problem with variable number of combined 1+1 dedicated and shared connections. The inventive method enables a solution in time that is polynomial of the input size. Thus, the time complexity of the joint-optimization method is significantly less than that of existing methods.Type: ApplicationFiled: August 17, 2012Publication date: August 22, 2013Applicant: NEC LABORATORIES AMERICA, INC.Inventors: Ankitkumar N. Patel, Philip Nan Ji, Yoshiaki Aono, Daisuke Taniguchi
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Publication number: 20120105671Abstract: An image processing device includes: a first interpolation unit that performs interpolation using pixel information of pixels having a color same as a color of a pixel of attention and present around the pixel of attention; a second interpolation unit that interpolates color information lost in the pixel of attention using color information of the pixels around the pixel of attention; a combining unit that combines outputs of the first and second interpolation units; a first filter that includes a first filter frequency characteristic and detects a first image of a first region; a second filter that includes a second filter frequency characteristic and detects a second image of a second region; and a combination-ratio generating unit that generates a value for determining a combination ratio of the outputs of the first and second interpolation units in the combining unit.Type: ApplicationFiled: October 12, 2011Publication date: May 3, 2012Inventors: Daisuke TANIGUCHI, Manabu KAWASHIMA
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Publication number: 20110006917Abstract: A parking aid system is disclosed. The parking aid system includes: a parking space borderline recognition section configured to recognize two borderlines of the parking space based on a captured image, which is captured by an imaging device mounted to the vehicle, the two borderlines respectively being two parts of the parking space boundary opposite to each other in a width direction of the parking space; a displacement calculation section configured to calculate displacement of the vehicle in the width direction with respect to the two borderlines based on positions of the two borderlines in the captured image and an imaging range of the imaging device; and a notifier configured to notify the displacement calculated by the displacement calculation section.Type: ApplicationFiled: June 8, 2010Publication date: January 13, 2011Applicant: DENSO CORPORATIONInventors: Daisuke Taniguchi, Ryusuke Kawano