Patents by Inventor Daisuke Tohyama

Daisuke Tohyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5844268
    Abstract: A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: December 1, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichiro Noda, Daisuke Tohyama
  • Patent number: 5702966
    Abstract: A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.
    Type: Grant
    Filed: October 16, 1996
    Date of Patent: December 30, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichiro Noda, Daisuke Tohyama
  • Patent number: 5596529
    Abstract: A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: January 21, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichiro Noda, Daisuke Tohyama
  • Patent number: 5532181
    Abstract: According to this invention, a semiconductor non-volatile memory device includes a semiconductor substrate, insulating films formed on the semiconductor substrate and having at least two types of gate insulating films having different thicknesses and a first conductive film formed on the insulating films and electrically floating from the semiconductor substrate through the insulating films. These at least two types of gate insulating films include a first insulating film formed on said semiconductor substrate and a first diffusion layer of a conductivity type and a second insulating film formed on said semiconductor substrate and a second diffusion layer, of the opposite conductivity type, which is isolated from the first diffusion layer. The first conductive film is formed on the first and second insulating films.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: July 2, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Takebuchi, Daisuke Tohyama, Hidemitsu Ogura
  • Patent number: 5324972
    Abstract: According to this invention, a semiconductor non-volatile memory device includes a semiconductor substrate, insulating films formed on the semiconductor substrate and having at least two types of gate insulating films having different thicknesses and a first conductive film formed on the insulating films and electrically floating from the semiconductor substrate through the insulating films. These at least two types of gate insulating films include a first insulating film formed on said semiconductor substrate and a first diffusion layer of a conductivity type and a second insulating film formed on said semiconductor substrate and a second diffusion layer, of the opposite conductivity type, which is isolated from the first diffusion layer. The first conductive film is formed on the first and second insulating films.
    Type: Grant
    Filed: December 8, 1992
    Date of Patent: June 28, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Takebuchi, Daisuke Tohyama, Hidemitsu Ogura