Patents by Inventor Daisuke Tsunami
Daisuke Tsunami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136439Abstract: A semiconductor device includes a substrate, a semiconductor layer, an element region, and fin transistors. The substrate includes a principal surface. The semiconductor layer is formed as a surface layer or on the principal surface of the substrate, the surface layer being the principal surface of the substrate. The semiconductor layer has a crystal structure in which an angle between two of crystal orientations with equivalent relationships on a crystal plane having a correspondence with the principal surface of the substrate is 60 degrees or 120 degrees. The element region includes unit element regions formed on the principal surface of the substrate. The fin transistors are formed in the semiconductor layer, in the respective unit element regions. The fin transistors radially extend from a center toward an outer periphery of the element region. Adjacent two of the fin transistors have a spacing with a 60° angle or a 120° angle.Type: ApplicationFiled: March 22, 2021Publication date: April 25, 2024Applicant: Mitsubishi Electric CorporationInventors: Yuki TAKIGUCHI, Eiji YAGYU, Kunihiko NISHIMURA, Hisashi SAITO, Takahiro YAMADA, Daisuke TSUNAMI, Marika NAKAMURA, Masanao ITO
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Publication number: 20230326758Abstract: A substrate (1) having a GaN surface (2) is immersed in a catalyst metal solution (4) containing potassium hydroxide and a plating catalyst metal salt while being irradiated with ultraviolet light to deposit a catalyst metal (5) on the GaN surface (2). A metal film (7) is formed on the GaN surface (2) having the catalyst metal (5) deposited thereon by electroless plating.Type: ApplicationFiled: January 27, 2021Publication date: October 12, 2023Applicant: Mitsubishi Electric CorporationInventors: Koichiro NISHIZAWA, Daisuke TSUNAMI
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Publication number: 20220223558Abstract: A semiconductor device according to the invention of the present application includes a support, a semiconductor chip provided on the support and a die bond material for bonding a back surface of the semiconductor chip to the support, wherein a plurality of cutouts is formed at edges formed between the back surface and side surfaces of the semiconductor chip connected to the back surface, and the die bond material is provided integrally over the plurality of cutouts.Type: ApplicationFiled: August 27, 2019Publication date: July 14, 2022Applicant: Mitsubishi Electric CorporationInventors: Tomoyuki ASADA, Eri FUKUDA, Daisuke TSUNAMI
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Patent number: 11205704Abstract: Because of inclusion of: a source electrode that is formed on a front surface of a semiconductor substrate and that is joined to the semiconductor substrate both at a source electrode as a first contact region that is an ohmic contact region and at a source electrode as a second contact region that is a contact region with a non-ohmic contact or the like; a back-surface electrode formed on a back surface of the semiconductor substrate; and a through hole in which an interconnection is provided that connects the source electrode as the second contact region in the source electrode with the back-surface electrode; it is possible not only to improve the corrosion resistance but also to reduce the leakage current, so that a highly-reliable semiconductor device suited for high frequency operation is provided.Type: GrantFiled: February 1, 2018Date of Patent: December 21, 2021Assignee: Mitsubishi Electric CorporationInventor: Daisuke Tsunami
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Patent number: 11121034Abstract: There is provided a method of manufacturing a semiconductor device that is suitable for forming a one-step tapered groove even when a substrate material is a difficult-to-etch material. The method of manufacturing a semiconductor device includes a metal mask forming step, a dry etching step, and a metal mask removing step. The metal mask formation step forms a tapered metal mask having an opening on the back surface of the substrate. The opening exposes a part in the back surface, and an edge portion of the opening has a forward taper to the back surface. The dry etching step forms a tapered groove on the substrate by performing, from an upper side of the tapered metal mask, dry etching on the edge portion of the opening and the substrate exposed from the opening. The metal mask removing step removes the tapered metal mask.Type: GrantFiled: March 24, 2017Date of Patent: September 14, 2021Assignee: Mitsubishi Electric CorporationInventor: Daisuke Tsunami
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Publication number: 20210175337Abstract: Because of inclusion of: a source electrode that is formed on a front surface of a semiconductor substrate and that is joined to the semiconductor substrate both at a source electrode as a first contact region that is an ohmic contact region and at a source electrode as a second contact region that is a contact region with a non-ohmic contact or the like; a back-surface electrode formed on a back surface of the semiconductor substrate; and a through hole in which an interconnection is provided that connects the source electrode as the second contact region in the source electrode with the back-surface electrode; it is possible not only to improve the corrosion resistance but also to reduce the leakage current, so that a highly-reliable semiconductor device suited for high frequency operation is provided.Type: ApplicationFiled: February 1, 2018Publication date: June 10, 2021Applicant: Mitsubishi Electric CorporationInventor: Daisuke TSUNAMI
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Publication number: 20210173236Abstract: The present invention includes a step for depositing an active layer, a cladding layer, and a contact layer on a semiconductor substrate, a step for etching the layers to form a mesa structure, a step for forming an insulation film to cover the mesa structure, a step for reducing the thickness of the insulation film until the top surface of the contact layer is exposed and using the remaining insulation film as a side wall, a step for forming a dielectric resin layer and burying the mesa structure and the side wall, a step for selectively etching the dielectric resin layer to form an opening and causing the top surface of the contact layer to be exposed, and a step for forming an electrode in the opening.Type: ApplicationFiled: August 1, 2018Publication date: June 10, 2021Applicant: Mitsubishi Electric CorporationInventors: Keigo FUKUNAGA, Yuichiro HORIGUCHI, Kazuhiro MAEDA, Daisuke TSUNAMI
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Publication number: 20200098634Abstract: There is provided a method of manufacturing a semiconductor device that is suitable for forming a one-step tapered groove even when a substrate material is a difficult-to-etch material. The method of manufacturing a semiconductor device includes a metal mask forming step, a dry etching step, and a metal mask removing step. The metal mask formation step forms a tapered metal mask having an opening on the back surface of the substrate. The opening exposes a part in the back surface, and an edge portion of the opening has a forward taper to the back surface. The dry etching step forms a tapered groove on the substrate by performing, from an upper side of the tapered metal mask, dry etching on the edge portion of the opening and the substrate exposed from the opening. The metal mask removing step removes the tapered metal mask.Type: ApplicationFiled: March 24, 2017Publication date: March 26, 2020Applicant: Mitsubishi Electric CorporationInventor: Daisuke TSUNAMI
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Patent number: 9153942Abstract: A method of manufacturing a semiconductor device, includes forming a laser section on a portion of a substrate, the laser section including an active layer, an upper semiconductor layer on the active layer, and a mask on the upper semiconductor layer; forming a compound semiconductor layer of an indium-containing material in contact with a side of the laser section, the compound semiconductor layer having a projection immediately adjacent the laser section; and wet etching and removing the projection with an etchant containing hydrobromic acid and acetic acid, planarizing the compound semiconductor layer, and producing a (111)A surface in the upper semiconductor layer, under the mask.Type: GrantFiled: April 8, 2014Date of Patent: October 6, 2015Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Daisuke Tsunami, Hiroyuki Kawahara, Takashi Nagira
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Publication number: 20150244152Abstract: A method of manufacturing a semiconductor device, includes forming a laser section on a portion of a substrate, the laser section including an active layer, an upper semiconductor layer on the active layer, and a mask on the upper semiconductor layer; forming a compound semiconductor layer of an indium-containing material in contact with a side of the laser section, the compound semiconductor layer having a projection immediately adjacent the laser section; and wet etching and removing the projection with an etchant containing hydrobromic acid and acetic acid, planarizing the compound semiconductor layer, and producing a (111)A surface in the upper semiconductor layer, under the mask.Type: ApplicationFiled: April 8, 2014Publication date: August 27, 2015Applicant: Mitsubishi Electric CorporationInventors: Daisuke Tsunami, Hiroyuki Kawahara, Takashi Nagira
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Patent number: 9048295Abstract: A method of manufacturing a semiconductor device includes the steps of immersing a substrate in a solution containing metal ions to adhere a metal catalyst to a surface of the substrate, immersing the substrate with the metal catalyst adhered thereto in an electroless plating solution to electrolessly plate a layer on the substrate, immersing the substrate in an electroplating solution to electroplate a layer on the electrolessly plated layer using the electrolessly plated layer as a power feeding layer, and forming a metal layer of Cu or Ag on the electroplated layer. The electroplated layer is formed of a different material than the metal layer.Type: GrantFiled: August 27, 2013Date of Patent: June 2, 2015Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Daisuke Tsunami, Koichiro Nishizawa
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Publication number: 20140117549Abstract: A method of manufacturing a semiconductor device includes the steps of immersing a substrate in a solution containing metal ions to adhere a metal catalyst to a surface of the substrate, immersing the substrate with the metal catalyst adhered thereto in an electroless plating solution to electrolessly plate a layer on the substrate, immersing the substrate in an electroplating solution to electroplate a layer on the electrolessly plated layer using the electrolessly plated layer as a power feeding layer, and forming a metal layer of Cu or Ag on the electroplated layer. The electroplated layer is formed of a different material than the metal layer.Type: ApplicationFiled: August 27, 2013Publication date: May 1, 2014Applicant: Mitsubishi Electric CorporationInventors: Daisuke Tsunami, Koichiro Nishizawa