Patents by Inventor Daisuke Tsunami

Daisuke Tsunami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136439
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, an element region, and fin transistors. The substrate includes a principal surface. The semiconductor layer is formed as a surface layer or on the principal surface of the substrate, the surface layer being the principal surface of the substrate. The semiconductor layer has a crystal structure in which an angle between two of crystal orientations with equivalent relationships on a crystal plane having a correspondence with the principal surface of the substrate is 60 degrees or 120 degrees. The element region includes unit element regions formed on the principal surface of the substrate. The fin transistors are formed in the semiconductor layer, in the respective unit element regions. The fin transistors radially extend from a center toward an outer periphery of the element region. Adjacent two of the fin transistors have a spacing with a 60° angle or a 120° angle.
    Type: Application
    Filed: March 22, 2021
    Publication date: April 25, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuki TAKIGUCHI, Eiji YAGYU, Kunihiko NISHIMURA, Hisashi SAITO, Takahiro YAMADA, Daisuke TSUNAMI, Marika NAKAMURA, Masanao ITO
  • Publication number: 20230326758
    Abstract: A substrate (1) having a GaN surface (2) is immersed in a catalyst metal solution (4) containing potassium hydroxide and a plating catalyst metal salt while being irradiated with ultraviolet light to deposit a catalyst metal (5) on the GaN surface (2). A metal film (7) is formed on the GaN surface (2) having the catalyst metal (5) deposited thereon by electroless plating.
    Type: Application
    Filed: January 27, 2021
    Publication date: October 12, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Koichiro NISHIZAWA, Daisuke TSUNAMI
  • Publication number: 20220223558
    Abstract: A semiconductor device according to the invention of the present application includes a support, a semiconductor chip provided on the support and a die bond material for bonding a back surface of the semiconductor chip to the support, wherein a plurality of cutouts is formed at edges formed between the back surface and side surfaces of the semiconductor chip connected to the back surface, and the die bond material is provided integrally over the plurality of cutouts.
    Type: Application
    Filed: August 27, 2019
    Publication date: July 14, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tomoyuki ASADA, Eri FUKUDA, Daisuke TSUNAMI
  • Patent number: 11205704
    Abstract: Because of inclusion of: a source electrode that is formed on a front surface of a semiconductor substrate and that is joined to the semiconductor substrate both at a source electrode as a first contact region that is an ohmic contact region and at a source electrode as a second contact region that is a contact region with a non-ohmic contact or the like; a back-surface electrode formed on a back surface of the semiconductor substrate; and a through hole in which an interconnection is provided that connects the source electrode as the second contact region in the source electrode with the back-surface electrode; it is possible not only to improve the corrosion resistance but also to reduce the leakage current, so that a highly-reliable semiconductor device suited for high frequency operation is provided.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 21, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Daisuke Tsunami
  • Patent number: 11121034
    Abstract: There is provided a method of manufacturing a semiconductor device that is suitable for forming a one-step tapered groove even when a substrate material is a difficult-to-etch material. The method of manufacturing a semiconductor device includes a metal mask forming step, a dry etching step, and a metal mask removing step. The metal mask formation step forms a tapered metal mask having an opening on the back surface of the substrate. The opening exposes a part in the back surface, and an edge portion of the opening has a forward taper to the back surface. The dry etching step forms a tapered groove on the substrate by performing, from an upper side of the tapered metal mask, dry etching on the edge portion of the opening and the substrate exposed from the opening. The metal mask removing step removes the tapered metal mask.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: September 14, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Daisuke Tsunami
  • Publication number: 20210175337
    Abstract: Because of inclusion of: a source electrode that is formed on a front surface of a semiconductor substrate and that is joined to the semiconductor substrate both at a source electrode as a first contact region that is an ohmic contact region and at a source electrode as a second contact region that is a contact region with a non-ohmic contact or the like; a back-surface electrode formed on a back surface of the semiconductor substrate; and a through hole in which an interconnection is provided that connects the source electrode as the second contact region in the source electrode with the back-surface electrode; it is possible not only to improve the corrosion resistance but also to reduce the leakage current, so that a highly-reliable semiconductor device suited for high frequency operation is provided.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 10, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventor: Daisuke TSUNAMI
  • Publication number: 20210173236
    Abstract: The present invention includes a step for depositing an active layer, a cladding layer, and a contact layer on a semiconductor substrate, a step for etching the layers to form a mesa structure, a step for forming an insulation film to cover the mesa structure, a step for reducing the thickness of the insulation film until the top surface of the contact layer is exposed and using the remaining insulation film as a side wall, a step for forming a dielectric resin layer and burying the mesa structure and the side wall, a step for selectively etching the dielectric resin layer to form an opening and causing the top surface of the contact layer to be exposed, and a step for forming an electrode in the opening.
    Type: Application
    Filed: August 1, 2018
    Publication date: June 10, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Keigo FUKUNAGA, Yuichiro HORIGUCHI, Kazuhiro MAEDA, Daisuke TSUNAMI
  • Publication number: 20200098634
    Abstract: There is provided a method of manufacturing a semiconductor device that is suitable for forming a one-step tapered groove even when a substrate material is a difficult-to-etch material. The method of manufacturing a semiconductor device includes a metal mask forming step, a dry etching step, and a metal mask removing step. The metal mask formation step forms a tapered metal mask having an opening on the back surface of the substrate. The opening exposes a part in the back surface, and an edge portion of the opening has a forward taper to the back surface. The dry etching step forms a tapered groove on the substrate by performing, from an upper side of the tapered metal mask, dry etching on the edge portion of the opening and the substrate exposed from the opening. The metal mask removing step removes the tapered metal mask.
    Type: Application
    Filed: March 24, 2017
    Publication date: March 26, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Daisuke TSUNAMI
  • Patent number: 9153942
    Abstract: A method of manufacturing a semiconductor device, includes forming a laser section on a portion of a substrate, the laser section including an active layer, an upper semiconductor layer on the active layer, and a mask on the upper semiconductor layer; forming a compound semiconductor layer of an indium-containing material in contact with a side of the laser section, the compound semiconductor layer having a projection immediately adjacent the laser section; and wet etching and removing the projection with an etchant containing hydrobromic acid and acetic acid, planarizing the compound semiconductor layer, and producing a (111)A surface in the upper semiconductor layer, under the mask.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: October 6, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Daisuke Tsunami, Hiroyuki Kawahara, Takashi Nagira
  • Publication number: 20150244152
    Abstract: A method of manufacturing a semiconductor device, includes forming a laser section on a portion of a substrate, the laser section including an active layer, an upper semiconductor layer on the active layer, and a mask on the upper semiconductor layer; forming a compound semiconductor layer of an indium-containing material in contact with a side of the laser section, the compound semiconductor layer having a projection immediately adjacent the laser section; and wet etching and removing the projection with an etchant containing hydrobromic acid and acetic acid, planarizing the compound semiconductor layer, and producing a (111)A surface in the upper semiconductor layer, under the mask.
    Type: Application
    Filed: April 8, 2014
    Publication date: August 27, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Daisuke Tsunami, Hiroyuki Kawahara, Takashi Nagira
  • Patent number: 9048295
    Abstract: A method of manufacturing a semiconductor device includes the steps of immersing a substrate in a solution containing metal ions to adhere a metal catalyst to a surface of the substrate, immersing the substrate with the metal catalyst adhered thereto in an electroless plating solution to electrolessly plate a layer on the substrate, immersing the substrate in an electroplating solution to electroplate a layer on the electrolessly plated layer using the electrolessly plated layer as a power feeding layer, and forming a metal layer of Cu or Ag on the electroplated layer. The electroplated layer is formed of a different material than the metal layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 2, 2015
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Daisuke Tsunami, Koichiro Nishizawa
  • Publication number: 20140117549
    Abstract: A method of manufacturing a semiconductor device includes the steps of immersing a substrate in a solution containing metal ions to adhere a metal catalyst to a surface of the substrate, immersing the substrate with the metal catalyst adhered thereto in an electroless plating solution to electrolessly plate a layer on the substrate, immersing the substrate in an electroplating solution to electroplate a layer on the electrolessly plated layer using the electrolessly plated layer as a power feeding layer, and forming a metal layer of Cu or Ag on the electroplated layer. The electroplated layer is formed of a different material than the metal layer.
    Type: Application
    Filed: August 27, 2013
    Publication date: May 1, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Daisuke Tsunami, Koichiro Nishizawa