Abstract: A printed circuit board test assisting apparatus includes an input part that has the attribute information of the wiring pattern input thereto; a degradation degree process part that obtains a degradation degree in signal characteristics in a wiring pattern corresponding to attribute information that is input to the input part, based on position information of the wiring pattern corresponding to the attribute information input to the input part, the position information and the size information of the pattern removed area, and the degradation degree information; and an extracting process part that extracts for an actual measurement test a wiring pattern that has a degradation degree equal to or more than a predetermined degree, from wiring patterns for which degradation degrees have been obtained by the degradation degree process part.

Abstract: A wire-spacing verification method for a computer includes calculating a characteristic impedance of each wire model disposed in a substrate model on a basis of a propagation rate of a signal in the wire model and rise time or fall time of an element model for transmitting the signal, calculating a reference impedance for predetermined sections, creating a distribution map in a direction of a section length with respect to the characteristic impedance of each of the sections for which the reference impedance is calculated, calculating an index indicating a degree of mismatch with the reference impedance, on a basis of the created distribution map, and making an approval/denial determination on the wire model on a basis of the index.

Abstract: A printed circuit board includes a through hole constituted by a hole penetrating through the front and rear surfaces of the printed circuit board. A fabrication method of the printed circuit board, includes applying conductive material plating to the inner wall surface of the hole to form a through hole electrically connecting the front and rear surfaces of the printed circuit board, and removing the conductive material plated on the hole inner wall surface at least at a portion between the front and rear surfaces of the printed circuit board is carried out to thereby fabricate a printed circuit board having a through hole electrically isolates the front surface of the printed circuit board from the rear surface thereof.

Abstract: A pin placement determining method includes calculating a waveform deterioration amount of wires from a noise amount of the wires and wiring loss of the wires, the wires being coupled to a connector on a printed board, comparing the calculated waveform deterioration amount of the wires to an evaluation criteria, evaluating the wires in which the waveform deterioration amount exceeds the evaluation criteria, and replacing corresponding pins of the connectors to which the wires that have been evaluated as exceeding the evaluation criteria are coupled with replacement pins of connectors that have a low noise amount.

Abstract: A wiring design assisting apparatus includes an input part that has attribute information of a wiring pattern input thereto; a degradation degree process part that obtains a degradation degree in signal characteristics of a wiring pattern corresponding to attribute information that is input to the input part, based on position information of the wiring pattern corresponding to the attribute information input to the input part, position information and size information of a pattern removed area, and the degradation degree information; and an extracting process part that extracts, for re-wiring, wiring patterns that have degradation degrees equal to or more than a predetermined degree, from wiring patterns for which degradation degrees have been obtained by the degradation degree process part.

Abstract: A signal transmission system evaluation apparatus acquires statistics about a variation in a characteristic value and a limit value of the characteristic value corresponding to a given range of variation, with respect to each of the characteristic values which represent characteristics of the components. The apparatus calculates a probability distribution with respect to each of the characteristic values, based on the statistic acquired, calculates an eye-opening of the signal transmission system in case that the characteristic value is the limit value, makes an adjustment of the limit value. The apparatus calculates a yield rate of the signal transmission system based on the probability distribution and the limit value.

Abstract: A center location of an eye pattern generated by superimposing waveform signal pieces cut out from a waveform signal generated by a simulator is calculated, and an arrangement of a mask as a quality evaluation criterion of the eye pattern on the center location is envisaged to calculate time coordinate values and voltage coordinate values of feature points included in the mask. First feature points not on a time axis is set as processing objects, and a margin in the voltage axis direction is calculated based on the voltage coordinate values of the first feature points and the voltage coordinate values of waveform signal piece parts associated with the first feature points. Second feature points on the time axis is set as processing objects, and a margin in the time axis direction is calculated based on the time coordinate values of the second feature points and the time coordinate values of waveform signal piece parts associated with the second feature points.

Abstract: A multi-layer printed wiring board includes a first insulating layer, a second insulating layer having a dissipation factor higher than a dissipation factor of the first insulating layer, a first conductive layer, and a first via connected to a lead wire in the first conductive layer. The first via includes a stub extending through the second insulating layer.

Abstract: A parameter acquisition section acquires model information about a waveform simulation model of a system of signal transmission, a first parameter of a waveform variation in a time direction in the system, and a second parameter of a waveform variation in an amplitude direction in the system. A first eye pattern calculation section calculates a first eye pattern of the system through a waveform simulation based on the model information acquired by the parameter acquisition section. A second eye pattern calculation section calculates, based on the first and second parameters acquired by the parameter acquisition section, a second eye pattern through processing of the first eye pattern calculated by the first eye pattern calculation section. And a transmission margin calculation section calculates, as a transmission margin, a positional relationship between a specific area and an aperture of the second eye pattern calculated by the second eye pattern calculation section.

Abstract: In order to make it possible to automatically execute a wiring process which satisfies not only a design condition but also design quality relating to an electric characteristic, according to the embodiment, an automatic wiring apparatus includes a design condition changing section for changing a design condition in accordance with priority information regarding the design condition where a wiring process which satisfies the design condition cannot be carried out by a first wiring processing section, a quality allowability decision section for deciding whether or not quality of a wiring region can be allowed where a wiring process which satisfies the design condition after the changing can be executed by a second wiring processing section and an outputting section for outputting a result of the wiring process of the wiring region by the second wiring processing section if it is decided that the quality of the wiring region can be allowed.

Abstract: A disclosed device includes a simulation apparatus which simulates a shift in signal characteristics occurring in a wiring pattern formed in a printed wiring board including a first database that stores wiring pattern attribute information and wiring pattern positional information, a second database storing solid lack portion size information and solid lack portion positional information, a third database that stores shift amount information relative to positional relationships between the wiring patterns and the solid lack portions, a shift amount processing unit configured to obtain the shift amount of the signal characteristics in the wiring pattern corresponding to the wiring pattern attribute information which is input based on the wiring pattern positional information corresponding to the wiring pattern attribute information which is input, the solid lack portion positional information, the solid lack portion size information, and the shift amount information.

Abstract: A wire-spacing verification method for a computer includes calculating a characteristic impedance of each wire model disposed in a substrate model on a basis of a propagation rate of a signal in the wire model and rise time or fall time of an element model for transmitting the signal, calculating a reference impedance for predetermined sections, creating a distribution map in a direction of a section length with respect to the characteristic impedance of each of the sections for which the reference impedance is calculated, calculating an index indicating a degree of mismatch with the reference impedance, on a basis of the created distribution map, and making an approval/denial determination on the wire model on a basis of the index.

Abstract: A pin placement determining method includes calculating a waveform deterioration amount of wires from a noise amount of the wires and wiring loss of the wires, the wires being coupled to a connector on a printed board, comparing the calculated waveform deterioration amount of the wires to an evaluation criteria, evaluating the wires in which the waveform deterioration amount exceeds the evaluation criteria, and replacing corresponding pins of the connectors to which the wires that have been evaluated as exceeding the evaluation criteria are coupled with replacement pins of connectors that have a low noise amount.

Abstract: A transmission characteristic adjustment device and the like that can carry out circuit adjustment before an error occurs, and has a transmission characteristic with high reliability without generating an error are provided. The device determines existence or non-existence of a difference with respect to confirmed data based on each phase of a multiphase clock, detects a window width in a time axis direction of receiving data based on a result of the determination and a phase of the multiphase clock, and evaluates a setting value of a circuit element of the transmission element or the reception element that has an influence on a receiving waveform based on a fluctuation of the detected window width, and changes the setting value of the circuit element of the transmission element or the reception element based on a result of the evaluation.

Abstract: A printed circuit board test assisting apparatus includes an input part that has the attribute information of the wiring pattern input thereto; a degradation degree process part that obtains a degradation degree in signal characteristics in a wiring pattern corresponding to attribute information that is input to the input part, based on position information of the wiring pattern corresponding to the attribute information input to the input part, the position information and the size information of the pattern removed area, and the degradation degree information; and an extracting process part that extracts for an actual measurement test a wiring pattern that has a degradation degree equal to or more than a predetermined degree, from wiring patterns for which degradation degrees have been obtained by the degradation degree process part.

Abstract: A disclosed device includes a simulation apparatus which simulates a shift in signal characteristics occurring in a wiring pattern formed in a printed wiring board including a first database that stores wiring pattern attribute information and wiring pattern positional information, a second database storing solid lack portion size information and solid lack portion positional information, a third database that stores shift amount information relative to positional relationships between the wiring patterns and the solid lack portions, a shift amount processing unit configured to obtain the shift amount of the signal characteristics in the wiring pattern corresponding to the wiring pattern attribute information which is input based on the wiring pattern positional information corresponding to the wiring pattern attribute information which is input, the solid lack portion positional information, the solid lack portion size information, and the shift amount information.

Abstract: A wiring design assisting apparatus includes an input part that has attribute information of a wiring pattern input thereto; a degradation degree process part that obtains a degradation degree in signal characteristics of a wiring pattern corresponding to attribute information that is input to the input part, based on position information of the wiring pattern corresponding to the attribute information input to the input part, position information and size information of a pattern removed area, and the degradation degree information; and an extracting process part that extracts, for re-wiring, wiring patterns that have degradation degrees equal to or more than a predetermined degree, from wiring patterns for which degradation degrees have been obtained by the degradation degree process part.

Abstract: The present invention relates to verification of a transmission margin of various transmission lines transmitting a signal such as a high-speed digital signal and ensures improved verification accuracy. A transmission margin verification apparatus according to the present invention is configured with a measurement unit (e.g., LSI tester 4, network analyzer 6, pulse generator 8, oscilloscope 10) operable to measure a transmission loss and a leading edge waveform of pseudo transmission lines (e.g., transmission lines 56, 62, 66) corresponding to a target device 44 to be verified, and a calculation unit (tester controller 12) operable to reference the transmission line loss and the leading edge waveform measured by the measurement unit, calculate a transmission waveform of the target device, and associate the transmission waveform with a mask of the target device to calculate a transmission margin of the target device.

Abstract: A multi-layer printed wiring board includes a first insulating layer, a second insulating layer having a dissipation factor higher than a dissipation factor of the first insulating layer, a first conductive layer, and a first via connected to a lead wire in the first conductive layer. The first via includes a stub extending through the second insulating layer.

Abstract: A center location of an eye pattern generated by superimposing waveform signal pieces cut out from a waveform signal generated by a simulator is calculated, and an arrangement of a mask as a quality evaluation criterion of the eye pattern on the center location is envisaged to calculate time coordinate values and voltage coordinate values of feature points included in the mask. First feature points not on a time axis is set as processing objects, and a margin in the voltage axis direction is calculated based on the voltage coordinate values of the first feature points and the voltage coordinate values of waveform signal piece parts associated with the first feature points. Second feature points on the time axis is set as processing objects, and a margin in the time axis direction is calculated based on the time coordinate values of the second feature points and the time coordinate values of waveform signal piece parts associated with the second feature points.