Patents by Inventor Daizo Andoh

Daizo Andoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7247508
    Abstract: A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes processes of: forming semiconductor electrodes at the semiconductor section; forming substrate electrodes at the circuit substrate; firstly affixing one part of the semiconductor section and circuit substrate to an intermediate connector made of insulating material; forming via holes at intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes; electrically connecting each semiconductor electrode and each substrate electrode via each via hole; and secondly affixing the other part of the semiconductor section and circuit substrate to the intermediate connector.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: July 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Higashitani, Tadashi Nakamura, Daizo Andoh
  • Patent number: 7174632
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Patent number: 7155820
    Abstract: The present invention provides a method of manufacturing a printed circuit board, which includes preparing a dielectric substrate, coating surfaces of the dielectric substrate, filling a via hole with a conductor, peeling mold-releasing films, compressing the dielectric substrate and forming metal foils. The dielectric substrate has patterned wiring layers on both surfaces, and the wiring layers are connected electrically with each other by the conductor. The dielectric substrate is made of a glass cloth or a glass nonwoven fabric impregnated with a thermosetting epoxy resin mixed with fine particles, and the conductive filler in the conductor has an average particle diameter larger than that of the fine particles. Accordingly, the printed circuit board has an improved moisture resistance as a whole and also excellent connection reliability and repair resistance. In addition, the dielectric substrate of the printed circuit board has an improved mechanical strength such as flexural rigidity.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: January 2, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Daizo Andoh, Fumio Echigo, Tadashi Nakamura, Yasuhiro Nakatani, Yoji Ueda, Tousaku Nishiyama, Shozo Ochi
  • Patent number: 7047629
    Abstract: A circuit board manufacturing method including the steps of forming a through hole on an insulator layer and then filling the through hole with a conductive paste; dispersing and forming a protective agent on an adhesion surface of a conductor foil so as to include adhesion surface regions where the protective agent does not exist; sticking the conductor foil to the insulator layer; and abutting a plurality of conductive powders constituting the conductive paste and the conductor foil to each other through the adhesion surface regions by means of heating and pressurizing the insulator layer and conductor foil.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: May 23, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Patent number: 6916706
    Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: July 12, 2005
    Assignee: Matsushita Electric Industrial Co, Ltd.
    Inventors: Fumio Echigo, Tadashi Nakamura, Daizo Andoh
  • Publication number: 20050142693
    Abstract: A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes processes of: forming semiconductor electrodes at the semiconductor section; forming substrate electrodes at the circuit substrate; firstly affixing one part of the semiconductor section and circuit substrate to an intermediate connector made of insulating material; forming via holes at intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes; electrically connecting each semiconductor electrode and each substrate electrode via each via hole; and secondly affixing the other part of the semiconductor section and circuit substrate to the intermediate connector.
    Type: Application
    Filed: February 23, 2005
    Publication date: June 30, 2005
    Inventors: Hideki Higashitani, Tadashi Nakamura, Daizo Andoh
  • Publication number: 20040201367
    Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 14, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumio Echigo, Tadashi Nakamura, Daizo Andoh
  • Publication number: 20040142161
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 22, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Patent number: 6756628
    Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumio Echigo, Tadashi Nakamura, Daizo Andoh
  • Patent number: 6753483
    Abstract: The present invention provides a printed circuit board, which includes a dielectric substrate having via holes formed in the thickness direction, and a conductor including a conductive filler is filled in the via holes. The dielectric substrate has patterned wiring layers on both surfaces, and the wiring layers are connected electrically with each other by the conductor. The dielectric substrate is made of a glass cloth or a glass nonwoven fabric impregnated with a thermosetting epoxy resin mixed with fine particles, and the conductive filler in the conductor has an average particle diameter larger than that of the fine particles. Accordingly, the printed circuit board has an improved moisture resistance as a whole and also excellent connection reliability and repair resistance. In addition, the dielectric substrate of the printed circuit board has an improved mechanical strength such as flexural rigidity. The present invention also provides a method of manufacturing such a printed circuit board.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: June 22, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Daizo Andoh, Fumio Echigo, Tadashi Nakamura, Yasuhiro Nakatani, Yoji Ueda, Tousaku Nishiyama, Shozo Ochi
  • Patent number: 6745464
    Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 8, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumio Echigo, Hideki Higashitani, Daizo Andoh, Noritake Fukuda, Yasuhiro Nakatani, Tadashi Nakamura
  • Publication number: 20040089471
    Abstract: The present invention provides a printed circuit board, which includes a dielectric substrate having via holes formed in the thickness direction, and a conductor including a conductive filler is filled in the via holes. The dielectric substrate has patterned wiring layers on both surfaces, and the wiring layers are connected electrically with each other by the conductor. The dielectric substrate is made of a glass cloth or a glass nonwoven fabric impregnated with a thermosetting epoxy resin mixed with fine particles, and the conductive filler in the conductor has an average particle diameter larger than that of the fine particles. Accordingly, the printed circuit board has an improved moisture resistance as a whole and also excellent connection reliability and repair resistance. In addition, the dielectric substrate of the printed circuit board has an improved mechanical strength such as flexural rigidity. The present invention also provides a method of manufacturing such a printed circuit board.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 13, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Daizo Andoh, Fumio Echigo, Tadashi Nakamura, Yasuhiro Nakatani, Yoji Ueda, Tousaku Nishiyama, Shozo Ochi
  • Patent number: 6734375
    Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
  • Publication number: 20040080918
    Abstract: A protective agent 6 for protecting a wiring 1 is dispersed and placed in mottle-like on an interface between a via 3 and a wiring layer 2. Then, each dimension of interface regions 7 where the protective agent 6 does not exist is set to such a size that a plurality of conductive powders 4 constituting the via 3 can abutted on the wiring layer 2. Therefore, the plurality of conductive powders 4 and the wiring layer 2 are abutted each other in each interface region 7 where the protective agent 6 does not exist to electrically connect, thereby stabilizing the connection resistance for a prolonged period of time.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 29, 2004
    Applicant: MUTSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Patent number: 6713688
    Abstract: A protective agent 6 for protecting a wiring 1 is dispersed and placed in mottle-like on an interface between a via 3 and a wiring layer 2. Then, each dimension of interface regions 7 where the protective agent 6 does not exist is set to such a size that a plurality of conductive powders 4 constituting the via 3 can abutted on the wiring layer 2. Therefore, the plurality of conductive powders 4 and the wiring layer 2 are abutted each other in each interface region 7 where the protective agent 6 does not exist to electrically connect, thereby stabilizing the connection resistance for a prolonged period of time.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: March 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinobu Kokufu, Takeshi Suzuki, Fumio Echigo, Daizo Andoh, Tatsuo Ogawa, Yoshihiro Kawakita, Satoru Tomekawa
  • Patent number: 6691409
    Abstract: A circuit board is configured so as to include not less than two wiring layers, an insulator layer for electric insulation between the wiring layers, and an inner-via-hole conductive member provided in the insulator layer in a thickness direction of the insulator layer, for electric connection between the wiring layers. The insulator layer is made of a composite material containing an organic resin and a material having a smaller thermal expansion coefficient than that of the organic resin, and includes a surface part, a core part, and a surface part laminated in the stated order, the surface part having a high content of the organic resin, the core part having a low content of the organic resin. The wiring layers have a land portion that is connected with the inner-via-hole conductive member, the land portion being embedded so as to be substantially in contact with the core part, and the inner-via-hole conductive member has a thickness substantially equal to a thickness of the core part.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: February 17, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Tatsuo Ogawa, Yoshihiro Bessho, Satoru Tomekawa, Yasuhiro Nakatani, Yoji Ueda, Susumu Matsuoka, Daizo Andoh, Fumio Echigo
  • Publication number: 20030188428
    Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.
    Type: Application
    Filed: March 31, 2003
    Publication date: October 9, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Fumio Echigo, Hideki Higashitani, Daizo Andoh, Noritake Fukuda, Yasuhiro Nakatani, Tadashi Nakamura
  • Patent number: 6546624
    Abstract: Removable mask films 303 are formed on the both sides of the substrate having the adhesive layer 302 by applying and drying a resin varnish 304 including a ultraviolet-absorbing agent, and fine through holes 306 are formed by using a third harmonics YAG solid-state laser light with a relatively short wavelength not longer than that in the ultraviolet range in such a way that the effects of such a residual strain as the conventional embodiment forming a removable mask film by a laminating process may be decreased as well as the more fine hole drilling compared with conventional embodiment using the carbon dioxide gas laser with a relatively long wavelength may be performed.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: April 15, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumio Echigo, Hideki Higashitani, Daizo Andoh, Noritake Fukuda, Yasuhiro Nakatani, Tadashi Nakamura
  • Publication number: 20030066683
    Abstract: A circuit board is configured so as to include not less than two wiring layers, an insulator layer for electric insulation between the wiring layers, and an inner-via-hole conductive member provided in the insulator layer in a thickness direction of the insulator layer, for electric connection between the wiring layers. The insulator layer is made of a composite material containing an organic resin and a material having a smaller thermal expansion coefficient than that of the organic resin, and includes a surface part, a core part, and a surface part laminated in the stated order, the surface part having a high content of the organic resin, the core part having a low content of the organic resin. The wiring layers have a land portion that is connected with the inner-via-hole conductive member, the land portion being embedded so as to be substantially in contact with the core part, and the inner-via-hole conductive member has a thickness substantially equal to a thickness of the core part.
    Type: Application
    Filed: October 25, 2002
    Publication date: April 10, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Tatsuo Ogawa, Yoshihiro Bessho, Satoru Tomekawa, Yasuhiro Nakatani, Yoji Ueda, Susumu Matsuoka, Daizo Andoh, Fumio Echigo
  • Patent number: 6518514
    Abstract: A circuit board is configured so as to include not less than two wiring layers, an insulator layer for electric insulation between the wiring layers, and an inner-via-hole conductive member provided in the insulator layer in a thickness direction of the insulator layer, for electric connection between the wiring layers. The insulator layer is made of a composite material containing an organic resin and a material having a smaller thermal expansion coefficient than that of the organic resin, and includes a surface part, a core part, and a surface part laminated in the stated order, the surface part having a high content of the organic resin, the core part having a low content of the organic resin. The wiring layers have a land portion that is connected with the inner-via-hole conductive member, the land portion being embedded so as to be substantially in contact with the core part, and the inner-via-hole conductive member has a thickness substantially equal to a thickness of the core part.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: February 11, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Suzuki, Tatsuo Ogawa, Yoshihiro Bessho, Satoru Tomekawa, Yasuhiro Nakatani, Yoji Ueda, Susumu Matsuoka, Daizo Andoh, Fumio Echigo