Patents by Inventor Daizo ICHIKAWA

Daizo ICHIKAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9123795
    Abstract: A method of manufacturing semiconductor wafers which facilitates formation of orientation flat lines and allows beveling work without problems. The method of manufacturing semiconductor wafers includes steps wherein a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method including: a marking step of forming straight groove-like orientation flat lines by a laser beam so as to cross the respective small-diameter wafers in each row in the large-diameter semiconductor wafer, wherein cutout positions of the small-diameter wafers are aligned in rows in a specific direction, collectively for each of the rows; and a cutting step of cutting out the small-diameter wafers separately from the large-diameter semiconductor wafer, by a laser beam, after the marking step, in such a way that the orientation flat lines are located at required positions in the small-diameter wafers to be obtained.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 1, 2015
    Assignees: FUJIKOSHI MACHINERY CORP., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yoshio Nakamura, Daizo Ichikawa, Haruo Sumizawa, Shiro Hara, Sommawan Khumpuang, Shinichi Ikeda
  • Publication number: 20140154870
    Abstract: A method of manufacturing semiconductor wafers is provided which facilitates formation of orientation flat lines and allows beveling work without problems. The method of manufacturing semiconductor wafers according to the present invention is a method of manufacturing semiconductor wafers, in which a plurality of small-diameter wafers is cut out from a large-diameter semiconductor wafer, the method including: a marking step of forming straight groove-like orientation flat lines by a laser beam so as to cross the respective small-diameter wafers in each row in the large-diameter semiconductor wafer, wherein cutout positions of the small-diameter wafers are aligned in rows in a specific direction, collectively for each of the rows; and a cutting step of cutting out the small-diameter wafers separately from the large-diameter semiconductor wafer by a laser beam after the marking step.
    Type: Application
    Filed: November 22, 2013
    Publication date: June 5, 2014
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, Fujikoshi Machinery Corp.
    Inventors: Yoshio NAKAMURA, Daizo ICHIKAWA, Haruo SUMIZAWA, Shiro HARA, Sommawan KHUMPUANG, Shinichi IKEDA