Patents by Inventor DAJIAN CUI

DAJIAN CUI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12368983
    Abstract: A readout circuit of a single photon avalanche focal plane includes a pixel array circuit, a serial bus circuit, a clock and timing control circuit, a working mode control circuit, a clock generation circuit, temperature sensing circuits, data processing and storage circuits, I/O driving circuits, and a uniformity correction circuit. The pixel array circuit includes pixel unit circuits arranged in an array. The uniformity correction circuit is configured to improve imaging uniformity by performing regional offset adjustment on the pixel array circuit. By adjusting pixels in abnormal areas or a global bias voltage through uniformity correction, a scale of an array of the pixel array circuit is improved, and an SPAD array chip is protected from strong light, so that the readout circuit well meets application scenarios with complex environmental information, high spatial resolution ratio and high imaging frame rate.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: July 22, 2025
    Assignee: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO 44 RESEARCH INSTITUTE
    Inventors: Shuiqing Xi, Ruoyao Gao, Dajian Cui, Junxiang Yuan
  • Publication number: 20240179437
    Abstract: A readout circuit of a single photon avalanche focal plane includes a pixel array circuit, a serial bus circuit, a clock and timing control circuit, a working mode control circuit, a clock generation circuit, temperature sensing circuits, data processing and storage circuits, I/O driving circuits, and a uniformity correction circuit. The pixel array circuit includes pixel unit circuits arranged in an array. The uniformity correction circuit is configured to improve imaging uniformity by performing regional offset adjustment on the pixel array circuit. By adjusting pixels in abnormal areas or a global bias voltage through uniformity correction, a scale of an array of the pixel array circuit is improved, and an SPAD array chip is protected from strong light, so that the readout circuit well meets application scenarios with complex environmental information, high spatial resolution ratio and high imaging frame rate.
    Type: Application
    Filed: July 18, 2023
    Publication date: May 30, 2024
    Inventors: SHUIQING XI, RUOYAO GAO, DAJIAN CUI, JUNXIANG YUAN