Patents by Inventor Da-Jiang Yang

Da-Jiang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7989804
    Abstract: A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interfaces. The test pattern structure of the present invention can detect the interconnection failure quickly and correctly without SEM identification.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: August 2, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Da-Jiang Yang, Chih-Ping Lee, Rui-Huang Cheng, Xing-Hua Zhang, Xu Ma, Xiao-Fei Han, Hong Ma, Hong Liao, Yuan-Li Ding
  • Publication number: 20100227131
    Abstract: A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interfaces. The test pattern structure of the present invention can detect the interconnection failure quickly and correctly without SEM identification.
    Type: Application
    Filed: March 4, 2009
    Publication date: September 9, 2010
    Applicant: United Microelectronics Corp.
    Inventors: Da-Jiang Yang, Chih-Ping Lee, Rui-Huang Cheng, Xing-Hua Zhang, Xu Ma, Xiao-Fei Han, Hong Ma, Hong Liao, Yuan-Li Ding
  • Publication number: 20090042388
    Abstract: A semiconductor substrate is first provided. The semiconductor substrate includes a material layer and a patterned photoresist layer disposed on the material layer. Subsequently, a contact etching process is performed on the material layer by utilizing the patterned photoresist layer as an etching mask so to form an etched hole in the material layer. Thereafter, a solvent cleaning process is carried out on the semiconductor substrate by utilizing a cleaning solvent. Next, a water cleaning process is performed on the semiconductor substrate by utilizing deionized water. The temperature of the deionized water is in a range from 30° C. to 99° C.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 12, 2009
    Inventors: Zhi-Qiang Sun, Tien-Cheng Lan, Hua-Kuo Lee, Jing-Hao Chen, Wen-Chun Huang, Run-Shun Wang, Jing-Ling Wang, Da-Jiang Yang, Chee-Siang Ong