Abstract: An optical phased board includes a plurality of optical waveguide layers and a plurality of isolation layers. Each optical waveguide layer includes a plurality of optical waveguides, and the optical waveguides are arranged side by side. The optical waveguide layers and the isolation layers are arranged in a superimposed manner, and each isolation layer is located between two adjacent optical waveguide layers. The optical phased board includes a two-dimensional optical waveguide array to perform two-dimensional beam scanning.

Abstract: Embodiments of this application provide a balance-unbalance conversion apparatus. The apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.

Abstract: Embodiments of this application provide a balance-unbalance conversion apparatus. The apparatus includes an insulation substrate, a first microstrip, a second microstrip, and a conductive ground. The first microstrip includes a first balance signal connection section, a first impedance matching section, and an unbalance signal connecting section. The unbalance signal connecting section is configured to transmit an unbalance signal. The second microstrip includes a second balance signal connecting section, a second impedance matching section, and a ground section. The second balance signal connecting section is configured to transmit a second component of the balance signal. The ground section is configured to connect to a ground signal. The first microstrip, the second microstrip, and the conductive ground are all disposed on the insulation substrate, and a cross-sectional area of at least a part of the first microstrip and/or at least a part of the second microstrip is gradient.

Abstract: An encoding method, an encoder, and a decoder for dynamic power consumption control are provided. The encoder includes a control unit, an initial encoding unit, and L incremental encoding units. The control unit is configured to enable only the initial encoding unit in an RS (N0, K) operating mode to perform encoding or enable only the initial encoding unit and first j incremental encoding units in the L incremental encoding units in an RS (Nj, K) operating mode to perform encoding. The initial encoding unit is configured to perform RS FEC encoding on m(x) to obtain a quotient D0(x) and a remainder R0(x) of xN0?Km(x) relative to g0(x). An (h+1)th incremental encoding unit is configured to obtain, according to a quotient Dh(x) and a remainder Rh(x), a quotient Dh+1(x) and a remainder Rh+1(x) of xNh+1?Km(x) relative to gh+1(x).

Abstract: An encoding method, an encoder, and a decoder for dynamic power consumption control are provided. The encoder includes a control unit, an initial encoding unit, and L incremental encoding units. The control unit is configured to enable only the initial encoding unit in an RS (N0, K) operating mode to perform encoding or enable only the initial encoding unit and first j incremental encoding units in the L incremental encoding units in an RS (Nj, K) operating mode to perform encoding. The initial encoding unit is configured to perform RS FEC encoding on m(x) to obtain a quotient D0(x) and a remainder R0(x) of xN0?Km(x) relative to g0(x). An (h+1)th incremental encoding unit is configured to obtain, according to a quotient Dh(x) and a remainder Rh(x), a quotient Dh+1(x) and a remainder Rh+1(x) of xNh+1?Km(x) relative to gh+1(x).

Abstract: The present embodiments provide a method and an apparatus for determining a frame boundary of an FEC frame, and a decoding system. The method includes receiving data, where the data includes N+P consecutive symbols, N consecutive symbols constitute a first data block, and N consecutive symbols constitute a second data block; obtaining s parameter values corresponding to the first data block. The method also includes determining a first iterative item and a second iterative item and determining, according to the s parameter values corresponding to the first data block, s parameter values corresponding to the second data block. Additionally, the method includes determining, according to the s parameter values corresponding to the second data block, whether the second symbol is a frame boundary of an FEC frame.

Abstract: The present application discloses a data processing method and apparatus. The technical solutions of the present application include: coding received data; distributing the coded data to multiple PCS lanes; and performing self-synchronizing scramble separately for multiple data streams distributed to the multiple PCS lanes, where the multiple data streams are in a one-to-one correspondence with the multiple PCS lanes. The technical solutions provided by the present application may be used to reduce occupied logical resources during a data processing process at a physical layer.

Abstract: The present embodiments provide a method and an apparatus for determining a frame boundary of an FEC frame, and a decoding system. The method includes receiving data, where the data includes N+P consecutive symbols, N consecutive symbols constitute a first data block, and N consecutive symbols constitute a second data block; obtaining s parameter values corresponding to the first data block. The method also includes determining a first iterative item and a second iterative item and determining, according to the s parameter values corresponding to the first data block, s parameter values corresponding to the second data block. Additionally, the method includes determining, according to the s parameter values corresponding to the second data block, whether the second symbol is a frame boundary of an FEC frame.

Abstract: The present application discloses a data processing method and apparatus. The technical solutions of the present application include: coding received data; distributing the coded data to multiple PCS lanes; and performing self-synchronizing scramble separately for multiple data streams distributed to the multiple PCS lanes, where the multiple data streams are in a one-to-one correspondence with the multiple PCS lanes. The technical solutions provided by the present application may be used to reduce occupied logical resources during a data processing process at a physical layer.

Abstract: A method and structure for switching data is provided. An output port scheduler obtains state information of VOQs and available state information of input port data channels and output port buffers. The output port scheduler sends scheduling request information to a FIC of an input port whose input port data channel is ready in input ports corresponding to non-empty VOQs pointing to an output port. After receiving the scheduling request information sent by the output port schedulers, the FIC of the selected input port selects to respond to a scheduling request of one output port scheduler, and sends the VOQ pointing to the output port in the selected input port to the output port buffer. The output port scheduler schedules the VOQ received by the output port buffer out of a switch chip. Buffer resources are saved and the switching performance is improved.

Abstract: A switching chassis includes more than one cascade unit and more than one switching unit, where: the cascade units have cascade interfaces to connect line processing chassis; the switching units have switching ports to connect the cascade interfaces; and any cascade interface of any cascade unit is connected to one switching port of any switching unit. A router cluster with the above switching chassis includes switching chassis and line processing chassis interconnected via optical fibers, where: any optical interface of any line processing chassis is connected to one cascade interface of any cascade unit; and any cascade interface of any cascade unit is connected to one switching port of any switching unit. With the present invention, the capacity of a router cluster can be expanded without the need to replace any component of the router cluster so that the expansion cost is lower.

Abstract: A method and structure for switching data is provided. An output port scheduler obtains state information of VOQs and available state information of input port data channels and output port buffers. The output port scheduler sends scheduling request information to a FIC of an input port whose input port data channel is ready in input ports corresponding to non-empty VOQs pointing to an output port. After receiving the scheduling request information sent by the output port schedulers, the FIC of the selected input port selects to respond to a scheduling request of one output port scheduler, and sends the VOQ pointing to the output port in the selected input port to the output port buffer. The output port scheduler schedules the VOQ received by the output port buffer out of a switch chip. Buffer resources are saved and the switching performance is improved.

Abstract: A switching chassis includes more than one cascade unit and more than one switching unit, where: the cascade units have cascade interfaces to connect line processing chassis; the switching units have switching ports to connect the cascade interfaces; and any cascade interface of any cascade unit is connected to one switching port of any switching unit. A router cluster with the above switching chassis includes switching chassis and line processing chassis interconnected via optical fibers, where: any optical interface of any line processing chassis is connected to one cascade interface of any cascade unit; and any cascade interface of any cascade unit is connected to one switching port of any switching unit. With the present invention, the capacity of a router cluster can be expanded without the need to replace any component of the router cluster so that the expansion cost is lower.

Abstract: A method and system of data communication, switching network board are disclosed. The data communication system includes multiple line card chassis, each including multiple line cards, at least one switching chip and at least one relay chip. The line card is respectively connected to the switching chip and the relay chip of the same line card chassis. The switching chip of one line card chassis is connected to the relay chip of at least one of other line card chassis. The relay chip of the one line card chassis is connected to the switching chip of the at least one of other line card chassis. The switching network board includes a switching chip and a relay chip. By implementing the above embodiments, the networking complexity is reduced, the networking cost is saved and the system reliability is enhanced in the case that a few line card chassis are cascaded.