Patents by Inventor Daksh Agarwal

Daksh Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047195
    Abstract: A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.
    Type: Application
    Filed: October 10, 2023
    Publication date: February 8, 2024
    Inventors: AKHIL MEHROTRA, VINAY SHANKAR VIDYARTHI, DAKSH AGARWAL, SAMANEH SADIGHI, JASON KENNEY, RAJINDER DHINDSA
  • Patent number: 11817312
    Abstract: A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: November 14, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Akhil Mehrotra, Vinay Shankar Vidyarthi, Daksh Agarwal, Samaneh Sadighi, Jason Kenney, Rajinder Dhindsa
  • Publication number: 20230230807
    Abstract: A method for controlling a critical dimension of a mask layer is described. The method includes receiving a first primary parameter level, a second primary parameter level, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The method also includes generating a primary signal having the first primary parameter level, and transitioning the primary signal from the first primary parameter level to the second primary parameter level. The method further includes generating a secondary radio frequency (RF) signal having the first secondary parameter level, and transitioning the secondary RF signal from the first secondary parameter level to the second secondary parameter level. The method includes transitioning the secondary RF signal from the second secondary parameter level to the third secondary parameter level.
    Type: Application
    Filed: February 25, 2022
    Publication date: July 20, 2023
    Inventors: Beibei Jiang, Taner Ozel, Chen Chen, Shuang Pi, Daksh Agarwal, Qing Xu, Merrett Wong, Amit Mukhopadhyay
  • Patent number: 10847368
    Abstract: A coating layer is deposited on a patterned feature on a first portion of a substrate. A second portion of the substrate outside the patterned feature is etched. The etching and the depositing are performed in a single pulsed plasma process using at least one of a pulsed source power signal and a pulsed bias power signal.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: November 24, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Byungkook Kong, Sangwook Kim, SeungHyun Park, Abhjeet Bagal, Kyoungjin Lee, Daksh Agarwal
  • Publication number: 20200135458
    Abstract: A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: AKHIL MEHROTRA, VINAY SHANKAR VIDYARTHI, DAKSH AGARWAL, SAMANEH SADIGHI, JASON KENNEY, RAJINDER DHINDSA
  • Publication number: 20180292756
    Abstract: A coating layer is deposited on a patterned feature on a first portion of a substrate. A second portion of the substrate outside the patterned feature is etched. The etching and the depositing are performed in a single pulsed plasma process using at least one of a pulsed source power signal and a pulsed bias power signal.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: Byungkook Kong, Sangwook Kim, SeungHyun Park, Abhijeet Bagal, Kyoungjin Lee, Daksh Agarwal