Patents by Inventor Daksh Agarwal
Daksh Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12695060Abstract: A method for controlling a critical dimension of a mask layer is described. The method includes receiving a first primary parameter level, a second primary parameter level, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The method also includes generating a primary signal having the first primary parameter level, and transitioning the primary signal from the first primary parameter level to the second primary parameter level. The method further includes generating a secondary radio frequency (RF) signal having the first secondary parameter level, and transitioning the secondary RF signal from the first secondary parameter level to the second secondary parameter level. The method includes transitioning the secondary RF signal from the second secondary parameter level to the third secondary parameter level.Type: GrantFiled: February 25, 2022Date of Patent: July 28, 2026Assignee: Lam Research CorporationInventors: Beibei Jiang, Taner Ozel, Chen Chen, Shuang Pi, Daksh Agarwal, Qing Xu, Merrett Wong, Amit Mukhopadhyay
-
Patent number: 12652973Abstract: A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.Type: GrantFiled: October 10, 2023Date of Patent: June 9, 2026Assignee: Applied Materials Inc.Inventors: Akhil Mehrotra, Vinay Shankar Vidyarthi, Daksh Agarwal, Samaneh Sadighi, Jason Kenney, Rajinder Dhindsa
-
Publication number: 20260090303Abstract: A method of forming features in stack with a silicon containing layer below a mask is provided. Features are etched into the stack. A post etch plasma treatment is provided to reduce surface roughness of sidewalls of the features.Type: ApplicationFiled: September 26, 2023Publication date: March 26, 2026Inventors: Daksh AGARWAL, Taner OZEL, Amit MUKHOPADHYAY, Qing XU, Merrett WONG
-
Publication number: 20250277148Abstract: A method of etching recessed features in stack with a silicon containing layer below a mask and over a wafer on a substrate support is provided. An etch gas comprising a carbon source, a fluorine source, and an organochloride source selected from the group consisting of carbon tetrachloride (CCI4), CxHyClz (where x>0 and z>0), and combinations thereof, is provided. The etch gas is formed into a plasma. The stack is exposed to the plasma to etch recessed features into the stack.Type: ApplicationFiled: May 3, 2023Publication date: September 4, 2025Inventors: Ilya PISKUN, Gregory Clinton VEBER, Daksh AGARWAL, Walter Thomas RALSTON, Amit MUKHOPADHYAY, Taner OZEL, Eric A. HUDSON, Qing XU, Merrett WONG
-
Publication number: 20250095964Abstract: A method for performing a plasma etch process is provided. The method initiates with receiving a substrate into a chamber. A high frequency (HF) RF signal is generated, said HF RF signal being pulsed in at least a three-state cycle including a first state, a second state, and a third state. The first state is configured at a first power level; the second state is configured at a second power level less than the first power level; and, the third state is configured at a third power level less than the second power level. The second power level of the HF RF signal being in the range of about 0 W to 3500 W. The HF RF signal is applied to an electrode of the chamber for performing the plasma etch process.Type: ApplicationFiled: December 19, 2022Publication date: March 20, 2025Inventors: Daksh AGARWAL, Beibei JIANG, Shuang PI, Chen CHEN, Taner OZEL, Qing XU, Merrett WONG, Amit MUKHOPADHYAY, Akanksha GUPTA, Taeseok OH
-
Publication number: 20240429063Abstract: A method of etching recessed features in a stack with a silicon containing layer over a wafer on a substrate support is provided. The substrate support is maintained at a temperature below about 30° C. An etch ga, comprising an organochloride source selected from the group consisting of carbon tetrachloride (CCl4), CxHyClz (where x>0 and z>0), and combinations thereof, a carbon source, a fluorine source, and a hydrogen source is flowed. The etch gas is formed into a plasma. The stack is exposed to the plasma to etch recessed features into the stack.Type: ApplicationFiled: November 1, 2022Publication date: December 26, 2024Inventors: Ilya PISKUN, Gregory Clinton VEBER, Daksh AGARWAL, Taner OZEL, Amit MUKHOPADHYAY, Chen CHEN, Andrew Clark SERINO, Eric HUDSON, Walter Thomas RALSTON, Qing XU, Merrett WONG
-
Publication number: 20240047195Abstract: A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.Type: ApplicationFiled: October 10, 2023Publication date: February 8, 2024Inventors: AKHIL MEHROTRA, VINAY SHANKAR VIDYARTHI, DAKSH AGARWAL, SAMANEH SADIGHI, JASON KENNEY, RAJINDER DHINDSA
-
Patent number: 11817312Abstract: A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.Type: GrantFiled: October 29, 2018Date of Patent: November 14, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Akhil Mehrotra, Vinay Shankar Vidyarthi, Daksh Agarwal, Samaneh Sadighi, Jason Kenney, Rajinder Dhindsa
-
Publication number: 20230230807Abstract: A method for controlling a critical dimension of a mask layer is described. The method includes receiving a first primary parameter level, a second primary parameter level, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The method also includes generating a primary signal having the first primary parameter level, and transitioning the primary signal from the first primary parameter level to the second primary parameter level. The method further includes generating a secondary radio frequency (RF) signal having the first secondary parameter level, and transitioning the secondary RF signal from the first secondary parameter level to the second secondary parameter level. The method includes transitioning the secondary RF signal from the second secondary parameter level to the third secondary parameter level.Type: ApplicationFiled: February 25, 2022Publication date: July 20, 2023Inventors: Beibei Jiang, Taner Ozel, Chen Chen, Shuang Pi, Daksh Agarwal, Qing Xu, Merrett Wong, Amit Mukhopadhyay
-
Patent number: 10847368Abstract: A coating layer is deposited on a patterned feature on a first portion of a substrate. A second portion of the substrate outside the patterned feature is etched. The etching and the depositing are performed in a single pulsed plasma process using at least one of a pulsed source power signal and a pulsed bias power signal.Type: GrantFiled: April 7, 2017Date of Patent: November 24, 2020Assignee: Applied Materials, Inc.Inventors: Byungkook Kong, Sangwook Kim, SeungHyun Park, Abhjeet Bagal, Kyoungjin Lee, Daksh Agarwal
-
Publication number: 20200135458Abstract: A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.Type: ApplicationFiled: October 29, 2018Publication date: April 30, 2020Inventors: AKHIL MEHROTRA, VINAY SHANKAR VIDYARTHI, DAKSH AGARWAL, SAMANEH SADIGHI, JASON KENNEY, RAJINDER DHINDSA
-
Publication number: 20180292756Abstract: A coating layer is deposited on a patterned feature on a first portion of a substrate. A second portion of the substrate outside the patterned feature is etched. The etching and the depositing are performed in a single pulsed plasma process using at least one of a pulsed source power signal and a pulsed bias power signal.Type: ApplicationFiled: April 7, 2017Publication date: October 11, 2018Inventors: Byungkook Kong, Sangwook Kim, SeungHyun Park, Abhijeet Bagal, Kyoungjin Lee, Daksh Agarwal