Abstract: A current mirror transistor is included in a tristate logic buffer circuit, with its base and emitter respectively connected to the base and emitter of the phase splitter transistor and its collector connected to the voltage supply terminal. The emitter size of the current mirror transistor is a multiple of the emitter size of the phase splitter transistor. A high resistance connected between the voltage supply terminal and the collector of the phase splitter transistor provides lower power consumption when the circuit is disabled; and the current mirror transistor supplements the drive current provided by the phase splitter transistor when the circuit is not disabled.

Abstract: A current mirror transistor is included in a tristate logic buffer circuit, with its base and emitter respectively connected to the base and emitter of the phase splitter transistor and its collector connected to the voltage supply terminal. A high resistance connected between the voltage supply terminal and the collector of the phase splitter transistor causes the circuit to consume less power when the circuit is disabled; and the current mirror transistor supplements the drive current provided by the phase splitter transistor when the circuit is not disabled.

Abstract: A novel integrated circuit memory cell structure where the individual cells in the storage matrix may be utilized as either a RAM type storage cell or a ROM type storage cell; this selective type storage cell is referred to as a programmable random access (PRAM). Each individual cell of the matrix comprises a write transistor, a read transistor, a RAM storage transistor, and a ROM floating gate storage transistor. Several different circuit arrangements for these four different transistors are shown in different embodiments of the invention.