Abstract: An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain.

Abstract: An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain.

Abstract: An integrated circuit includes an array of memory cells, addressing circuitry, and timing and control logic. The array of memory cells is configured to store data bits. The addressing circuitry is configured to address multiple locations of memory cells in response to a clock signal. The timing and control logic is responsive to the clock signal and configured to control a read-modify-write operation to read a first group of data bits from a first address location, modify at least one of the bits of the first group, and write the modified first group to the first address location. The read-modify-write operation is performed within one cycle of the clock signal.

Abstract: An apparatus for the on-chip testing of random access memory arrays. In representative embodiments, embedded circuitry provides the ability to test random access memory arrays on-chip without requiring substantial area on the chip. The circuits are inherently located closer to the tested area which reduces propagation delay errors. These advantages have been obtained by locating the circuitry necessary to perform such test in the addressing and input/output blocks of the RAM.

Abstract: An apparatus for the on-chip, soft repair of random access memory arrays. In representative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

Abstract: A method and apparatus operable to provide pseudo 2-port RAM functionality using 1-port memory cells. A pseudo 2-port RAM functionality is provided using an array of 1-port memory cells to perform read and write operations during a single clock cycle. Control logic is used to determine when the read and write operations occur. The pseudo 2-port RAM uses the control logic to divide the clock cycle into four phases in accordance with a preferred embodiment. The first phase is used to set up the addresses and register values, the second phase is used to prepare for the read operation, the third phase is used to perform the read operation and prepare for the write operation, and the fourth phase performs the write operation.

Abstract: An apparatus for the on-chip, soft repair of random access memory arrays. In representative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

Abstract: An apparatus for the on-chip, soft repair of random access memory arrays. In repesentative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

Abstract: An apparatus for the on-chip, soft repair of random access memory arrays. In repesentative embodiments, circuitry is disclosed which provides the ability to soft repair defective random access memory arrays. The disclosed techniques for repair of random access memory arrays do not use techniques such as laser repair in the removal of defective parts of the integrated circuit and its replacement with a redundant part. No additional processing steps are involved. The circuitry necessary to repair defects in random access memory arrays is included on-chip in the input/output blocks of the RAM.

Abstract: An apparatus for the on-chip testing random access memory arrays. In representative embodiments, circuitry is disclosed which provides the ability to test random access memory arrays on-chip by means that do not required substantial area on the chip. The circuits disclosed are inherently located closer to the tested area which reduces propagation delay errors. These advantages have been obtained by locating the circuitry necessary to perform such test in the addressing and input/output blocks of the RAM.

Abstract: A method and apparatus operable to provide pseudo 2-port RAM functionality using 1-port memory cells. A pseudo 2-port RAM functionality is provided using an array of 1-port memory cells to perform read and write operations during a single clock cycle. Control logic is used to determine when the read and write operations occur. The pseudo 2-port RAM uses the control logic to divide the clock cycle into four phases in accordance with a preferred embodiment. The first phase is used to set up the addresses and register values, the second phase is used to prepare for the read operation, the third phase is used to perform the read operation and prepare for the write operation, and the fourth phase performs the write operation.