Abstract: A palette for converting video data encoded in multiple YUV and RGB formats into a configuration suitable for transmission to a display and a multimedia system incorporating the same.

Abstract: Method and apparatus within a multimedia system for digitally decoding video pixel data. The pixel data is decoded to 24 bits per pixel from a compressed 8 bits per pixel format. The compressed pixel data is deformatted into its separate luminance and chrominance components. The components are then differentially expanded and assigned to associated pixel elements. Predominant color transitions are designated to determine the pixel location where the chrominance components change. An interpolated chrominance component may be inserted at these color change locations to smooth out the color transitions.

Abstract: Video control circuitry for controlling the video format presented to the cathode ray tube or screen and capable of providing a combination of character generation and cell generation along with other video types of control. The video controller may comprise a video memory means for controlling writing into and reading therefrom and means defining both a memory address and a memory data. There is a video data bus coupled to the video memory means and a processor address bus. A cathode ray tube controller has address lines and the address lines are connected to multiplexer means for selecting either the controller address lines or the processor lines. Control means are provided for controlling the multiplexer means so that in one state thereof the video memory means is addressed from the cathode ray tube controller means and in the other state the video memory means is addressed from the central processing unit address.

Abstract: Video control circuitry for controlling the video format presented to the cathode ray tube to provide a combination of character generation and cell generation along with selective character inversion on a character-by-character basis. The video controller may comprise a video memory means for storing video character codes, character generator means and cell generator means both being coupled from the output of the video memory means in a common to a shift register. The shift register has associated therewith controls for the loading thereof and for the shifting of signals therefrom. Control signal means are provided having a video inverting and a video non-inverting state. At the output of the shift register, there is preferably provided output gating means. The aforementioned control signals couple to the output gating means for providing either inversion or non-inversion of the signal to the output gating means from the shift register.

Abstract: Video control circuitry for controlling the video format presented to the cathod ray tube or screen and capable of providing a combination of character generation and cell generation along with other video types of control. The video controller may comprise a video memory means for controlling writing into and reading therefrom and means defining both a memory address and a memory data. There is a video data bus coupled to the video memory means and a processor address bus. A cathode ray tube controller has address lines and the address lines are connected to multiplexer means for selecting either the the controller address lines or the processor lines. Control means are provided for controlling the multiplexer means so that in one state thereof the video memory means is addressed from the cathode ray tube controller means and in the other state the video memory means is addressed from the central processing unit address.

Abstract: Data synchronization apparatus for a 1500 baud computer-audio frequency magnetic tape recorder interface is disclosed. The synchronization apparatus automatically detects bit cell boundaries and synchronizes at both the bit level and the byte level even if the audio waveform as read from the tape is inverted, as is the case with some tape recorders. Synchronization is performed by converting the audio waveform into a square wave and examining the square wave for predetermined pulse patterns. If one pattern is found, the positive-going edge of the waveform is selected as the bit cell boundary. If, on the other hand, another pattern is found, negative-going edges are selected as bit cell boundaries. Synchronization is achieved on a byte level by shifting incoming data into a first-in/first-out buffer and examining the stored data for a predetermined bit pattern.