Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

Abstract: A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.

Abstract: A method of fabricating a semiconductor structure includes forming a scissionable layer that is able to absorb infrared (IR) radiation, below a first carrier wafer. A first hard-dielectric layer is formed below the scissionable layer. A second hard-dielectric layer is formed on a top surface of a semiconductor wafer. The first dielectric layer is bonded with the second dielectric layer. Connectors on a bottom portion of the semiconductor wafer are formed to provide an electric connection to the semiconductor wafer. A second carrier wafer is connected to the connectors on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer with an IR, by passing the IR through the first carrier wafer. A back end of line (BEOL) wiring passing from a top surface of the semiconductor wafer through the first and second dielectric layers is provided.

Abstract: A method of fabricating a semiconductor structure includes forming a scissionable layer that is able to absorb infrared (IR) radiation, below a first carrier wafer. A first hard-dielectric layer is formed below the scissionable layer. A second hard-dielectric layer is formed on a top surface of a semiconductor wafer. The first dielectric layer is bonded with the second dielectric layer. Connectors on a bottom portion of the semiconductor wafer are formed to provide an electric connection to the semiconductor wafer. A second carrier wafer is connected to the connectors on the bottom portion of the semiconductor wafer. The first carrier wafer is separated from the semiconductor wafer by degrading the scissionable layer with an IR, by passing the IR through the first carrier wafer. A back end of line (BEOL) wiring passing from a top surface of the semiconductor wafer through the first and second dielectric layers is provided.

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips.

Abstract: An electrical connector or interposer for making connection in a high density device electronic environment. The connector is made of a high density array of nickel columns held in a layer of polyimide with each column extending beyond the opposing surfaces of said layer of polyimide. The connector may be used to make temporary or permanent connection to electrical contacts without alignment. Connection may be accomplished by loading forces sufficient to form either an indentation or a penetration of solder ball contacts. Contact to a single chip or a full wafer of chips is facilitated for testing.

Abstract: A multiple-chip probe assembly suitable for wafer testing over a wide temperature range includes a plurality of individual buckling beam probe elements. A support structure supports the plurality of buckling beam probe elements in an arrangement in accordance with an electrical contact footprint for use in electrically contacting multiple chips of a wafer under test and enables buckling movement in a contacting direction of the plurality of buckling beams. The support structure includes a principal support material having a thermal coefficient of expansion (TCE) matched with the wafer under test and a second material other than the principal support material, wherein a contact positioning of the plurality of buckling beam probe elements upon the wafer under test during a testing operation is maintained. The second material prevents an individual probe element from electrically contacting the principal support material.