Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.

Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.