Abstract: A debug port in accordance with the invention provides circuitry for enabling system (hardware and software) development within an inaccessible computer processor. In one embodiment, a debug port is incorporated within the internal logic of a single-chip, reduced instruction set signal processor referred to as the signal processor. A fully implemented debug port is comprised of five interacting functional elements: debug bus unit (DBU), debug command unit (DCU), debug instruction Unit (DIU), debug inject/extract unit (DJU), and a debug flow unit (DFU). The DBU provides circuitry for buffering data received from the signal processor and other functional elements within the debug port as well as accepting data from an external source. The DBU provides for off-chip connections. The DCU provides circuitry for decoding and executing debug commands received by the debug port. The DIU provides circuitry to insert one or more instructions with, or without, data into the instruction stream of the signal processor.

Abstract: The BRANCH DECISION ENCODING SCHEME shown herein overcomes the limitations of a dedicated debug port on a single chip computer processor. A dedicated debug port resolves many of the problems associated with an add-on logic analyzer, except for its limitation of an eight bit data interface. The 8 bit port is required as a trade-off between the device I/O requirements and development tools. During real time program development, it is virtually impossible to monitor the 24 bit program counter through a port only a third as wide. The present invention solves this problem by taking advantage of the sequential characteristics of application programs. There is a discontinuity in the program counter in only a limited number of situations: branches, jumps, subroutine calls and returns from subroutines, exceptions and returns from exceptions, traps and return from traps, and loopbacks to the tops of loops.

Abstract: The MODEM WITH DIGITAL ISOLATION removes the relatively large heavy isolation transformer from the Data Access Arrangement and substitutes two tiny pulse transformers between the Integrated Analog and Digital Signal Processor with multiplexers and demultiplexers to eliminate analog distortion and multiple leads, and to accommodate Lap Top/Palm Top computers, while enhancing data speeds. The combination with surge protection enables both uncommon and common mode protection.

Abstract: The ACTIVE SURGE REJECTION CIRCUIT uses a FET connected in one of the TIP and RING leads to open and close the lead. A JK flip-flop is connected to a voltage sensing circuit which senses voltage surges and clocks the flip-flop early in the voltage rise. This activates a first circuit to ground the FET gate and hold the FET open. Meanwhile, a second circuit comprising an RC circuit charges a capacitor which maintains the FET in its OFF condition for a period of time longer than the surge, i.e., about 1 m sec, and then clears the JK flip-flop after the capacitor has discharged a predetermined amount. This invention thus provides surge (noncommon mode) protection, and is especially useful in protecting modems from voltage surges while minimizing signal distortion during non-surge conditions.

Abstract: A range control system positioned within a stationary housing comprising: a pulse oscillator for providing a clock signal; and a transmitter receiver circuit that directionally transmits an acoustic pulse signal to a target and receives an echo from the target to provide an amplified echo signal. A timing circuit means is included for providing a range gate signal characterized to start with each clock signal and to have a predetermined duration characterized to provide a time for the acoustic pulse to travel to the target and for the echo to return from the target. An alarm signal is provided to indicate that an echo signal is being received prior to the termination of the range gate signal. A ring blanking gate signal source provides a ring blanking gate signal commencing with each clock signal and having a duration longer than the tailoff ringing of the acoustic pulse. A diode clamp is coupled to the transducer drive circuit echo signal output.

Abstract: A high frequency ballast circuit powered by a dc input voltage source for starting and operating a gas discharge lamp load, comprising: a means for providing drive signals, each the drive signal having a first and second state, a series switch having a conduction channel having a first and second terminal, the series switch having a control terminal responsive to the drive signals, the conduction channel is on (conductive) in responsive to the interval characterized by the first state of the drive signal and off (non-conductive) in response to a drive signal having a second state, and an inductor. A clamp diode is included. The inductor is coupled to the clamp diode cathode and to the series switch. A ballast reactance is included with a a power oscillator circuit, the power oscillator circuit has a transformer having, a primary winding having a first, a second and a center-tap terminal, a drive winding having a first and a second and a center-tap terminal, and an output winding.