Abstract: A cable solution which enables a flash controller which is located on a motherboard of an information processing system to be coupled with a memory socket which is located within a passive socket panel. In certain embodiments, a cable and header arrangement is provided for connecting the motherboard to the chassis socket panel card. This arrangement allows the front panel card to be simplified (i.e., to be a passive card). In certain embodiments, the solution uses a cable structure such as that used for integrated drive electronics (IDE) type disk drive cables or an ultra AT attachment (U-ATA) type cable. The cable solution provides a low cost solution which offers multiple performance options for a single cost. For example, the cable solution functions with both a standard memory card socket as well as a high speed memory card. Also, in certain embodiments, the header connections include ground signal paths interposed among the data signal paths.

Abstract: A method and apparatus is provided for processing tasks with failure recovery. The method includes storing one or more tasks in a queue, wherein each task has an associated exit routine, and determining at least one task to process based on a priority scheme. The method further includes processing the at least one task, and calling the exit routine based on determining that the task has not completed processing within a preselected period of time.

Abstract: A cable solution which enables a flash controller which is located on a motherboard of an information processing system to be coupled with a memory socket which is located within a passive socket panel. In certain embodiments, a cable and header arrangement is provided for connecting the motherboard to the chassis socket panel card. This arrangement allows the front panel card to be simplified (i.e., to be a passive card). In certain embodiments, the solution uses a cable structure such as that used for integrated drive electronics (IDE) type disk drive cables or an ultra AT attachment (U-ATA) type cable. The cable solution provides a low cost solution which offers multiple performance options for a single cost. For example, the cable solution functions with both a standard memory card socket as well as a high speed memory card. Also, in certain embodiments, the header connections include ground signal paths interposed among the data signal paths.

Abstract: The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.

Abstract: A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface coupled to the processor via an I/O link. The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor coupled to the I/O interface via a peripheral bus. The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.

Abstract: An integrated circuit, a computer system and a method of operating an computer system is disclosed. The method includes receiving a request for an authentication, at a microcontroller and requesting security data from a security device. The method also includes receiving the security data from the security device, at the microcontroller and evaluating the security data. The method also includes approving the authentication if the security data is evaluated as acceptable.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract: A method and apparatus is provided for processing tasks with failure recovery. The method includes storing one or more tasks in a queue, wherein each task has an associated exit routine, and determining at least one task to process based on a priority scheme. The method further includes processing the at least one task, and calling the exit routine based on determining that the task has not completed processing within a preselected period of time.

Abstract: A computer system including a bus bridge for bridging transactions between a secure execution mode-capable processor and a security services processor. The bus bridge may include a transaction source detector, a configuration header and control logic. The transaction source detector may receive a security initialization transaction performed as a result of execution of a security initialization instruction. Further, the transaction source detector may determine whether the secure execution mode-capable processor is a source of the security initialization transaction. The configuration header may provide storage of information associated with the security services processor. The control logic may determine whether the security services processor is coupled to the bus bridge via a non-enumerable, peripheral bus.

Abstract: Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.

Abstract: A method and apparatus is provided for processing tasks with failure recovery. The method includes storing one or more tasks in a queue, wherein each task has an associated exit routine, and determining at least one task to process based on a priority scheme. The method further includes processing the at least one task, and calling the exit routine based on determining that the task has not completed processing within a preselected period of time.

Abstract: A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches and the distributed memory system. Particularly, the computer system may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included. Probe commands may specify the source of the transaction as the receiving node for read transactions (such that dirty data is delivered to the source node from the node storing the dirty data).

Abstract: An integrated circuit, a computer system, and a method for authorizing RMCP requests. The method includes receiving a request for a system action and initiating a timer. The method also includes generating an authorization request for the system action and evaluating a result of the authorization request for the system action if received before an expiration of the timer. The method also includes granting the request for the system action if the expiration of the timer occurs before the result of the authorization request for the system action is received.

Abstract: A method and system for enhanced security and manageability using secure storage. The system may include a crypto-processor and a memory coupled to receive memory transactions through the crypto-processor. The memory transactions are passed to the memory by the crypto-processor. The system may include a first processor, a second processor coupled to the first processor, and a storage device operably coupled to the first processor through the second processor. The second processor is configured to control access to the storage device. The method includes transmitting a request for a memory transaction for a storage location in the storage device and receiving the request for the memory transaction at the crypto-processor. The method also includes determining if the memory transaction is authorized for the storage location, and passing the request for the memory transaction to the storage device if the memory transaction is authorized for the storage location.

Abstract: A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes a system memory configured to store data in a plurality of locations. The computer system also includes a memory controller which may selectively clear the data from a programmed range of the memory locations of the system memory when enabled in response to a reset of the processor.

Abstract: An integrated circuit, a client computer system, and a method for operating the integrated circuit in the client computer system. The integrated circuit includes a first bus interface logic for coupling to a first external bus, a microcontroller configured as an Alert Standard Format management engine, and a watchdog timer coupled to the microcontroller. The microcontroller is further configured to receive Alert Standard Format sensor data over the first external bus. The watchdog timer is coupled to receive a reset input upon a predetermined change in a system state. The watchdog timer is further configured to provide an indication to the microcontroller in response to an expiration of the watchdog timer.

Abstract: A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.

Abstract: A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

Abstract: A method an apparatus for providing capability information to a shared controller. In one embodiment, a peripheral bus host controller may be shared by a plurality of peripheral devices coupled to a peripheral bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may be configured to query the bus for peripheral devices by reading each address on the bus. During the querying process, the host controller may detect one or more peripheral devices coupled to the bus. Following the completion of the querying of the bus, the host controller may then begin reading configuration information from each of the detected devices. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device.

Abstract: A method and system for providing an external locking mechanism for memory locations. The memory includes a first plurality of storage locations configured with BIOS data and a second plurality of storage locations. The second plurality of storage locations includes a first plurality of blocks readable only in SMM and a second plurality of blocks readable in SMM and at least one operating mode other than SMM. The computer system includes a bus, a memory coupled to the bus, and a device coupled to access the memory over the bus. The memory includes a plurality of storage locations, divided into a plurality of memory units. The device includes one or more locks configured to control access to one or more of the plurality of memory units.