Patents by Inventor Dale E. Hoffman

Dale E. Hoffman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9740980
    Abstract: A tool and technique are employed to distill and prioritize multiple organizational (sub-system) capabilities based on ranked customer requirements or desires. A translational matrix is employed to organize preferences of the sub-system with respect to the customer requirements or desires. Relative importance scores are input into the matrix to reflect prioritized input versus prioritized capabilities. An adjusted relative importance score of the sub-system is automatically calculated and a resultant re-prioritization of sub-system attributes is created for application to new designs, services, or processes.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karl O. Casserly, Bohdan Demczar, Dale E. Hoffman, William P. Kostenko, John G. Torok
  • Patent number: 9740981
    Abstract: A tool and technique are employed to distill and prioritize multiple organizational (sub-system) capabilities based on ranked customer requirements or desires. A translational matrix is employed to organize preferences of the sub-system with respect to the customer requirements or desires. Relative importance scores are input into the matrix to reflect prioritized input versus prioritized capabilities. An adjusted relative importance score of the sub-system is automatically calculated and a resultant re-prioritization of sub-system attributes is created for application to new designs, services, or processes.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karl O. Casserly, Bohdan Demczar, Dale E. Hoffman, William P. Kostenko, John G. Torok
  • Publication number: 20150149483
    Abstract: A tool and technique are employed to distill and prioritize multiple organizational (sub-system) capabilities based on ranked customer requirements or desires. A translational matrix is employed to organize preferences of the sub-system with respect to the customer requirements or desires. Relative importance scores are input into the matrix to reflect prioritized input versus prioritized capabilities. An adjusted relative importance score of the sub-system is automatically calculated and a resultant re-prioritization of sub-system attributes is created for application to new designs, services, or processes.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl O. Casserly, Bohdan Demczar, Dale E. Hoffman, William P. Kostenko, John G. Torok
  • Publication number: 20150149485
    Abstract: A tool and technique are employed to distill and prioritize multiple organizational (sub-system) capabilities based on ranked customer requirements or desires. A translational matrix is employed to organize preferences of the sub-system with respect to the customer requirements or desires. Relative importance scores are input into the matrix to reflect prioritized input versus prioritized capabilities. An adjusted relative importance score of the sub-system is automatically calculated and a resultant re-prioritization of sub-system attributes is created for application to new designs, services, or processes.
    Type: Application
    Filed: October 14, 2014
    Publication date: May 28, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl O. Casserly, Bohdan Demczar, Dale E. Hoffman, William P. Kostenko, John G. Torok
  • Patent number: 6618844
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Patent number: 6618843
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Publication number: 20020040463
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Application
    Filed: June 29, 2001
    Publication date: April 4, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Publication number: 20020040467
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Application
    Filed: June 29, 2001
    Publication date: April 4, 2002
    Applicant: INTERNATION BUSINESS MACHINES CORPORATION
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Patent number: 6323050
    Abstract: A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: November 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Allan H. Dansky, Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman, Bhupindra Singh
  • Patent number: 5381421
    Abstract: A method, and apparatus for accomplishing the method, for controlling an operation of a test pin of a per-pin semiconductor device test system. The method includes the steps of, during a test cycle, generating a plurality of timing signals, providing a test pattern comprised of M-bits, and decoding the M-bits into one of 2.sup.M first multi-bit control words. In accordance with logical states of bits of the first control word, the method selects specified ones of the timing signals and generates a stimulus signal at a test pin in accordance with the selected specified ones of the timing signals. In accordance with an aspect of the invention, the step of providing provides test patterns at a rate of (x) test patterns per second, the step of generating generates test pin stimulus signals at a rate of (y) stimulus signals per second, and wherein (y)=n(x), where (n) is an integer greater than one.
    Type: Grant
    Filed: March 5, 1992
    Date of Patent: January 10, 1995
    Assignee: International Business Machines Corporation
    Inventors: John E. Dickol, Algirdas J. Gruodis, Dale E. Hoffman
  • Patent number: 5127011
    Abstract: Apparatus and method for controlling an operation of a test pin of a per-pin semiconductor device test system [10]. The apparatus includes pattern storage memory [42] for storing and for outputting information related to a state of the test pin for individual ones of a plurality of consecutive test cycles, pattern processor [14] having an input coupled to the pattern storage memory for generating for each of the test cycles words comprised of M bits, and a test pin control memory [18] having an input coupled to the output of the pattern processor for decoding each of the words into 2.sup.M or less command words. Each of the decoded command words includes a plurality of control bits. Predetermined ones of the plurality of control bits are coupled to pin driver electronics [24,28] for specifying, for each of the test cycles, at least one characteristic of an electrical signal transmitted to the test pin.
    Type: Grant
    Filed: January 12, 1990
    Date of Patent: June 30, 1992
    Assignee: International Business Machines Corporation
    Inventors: Michael L. Combs, Algirdas J. Gruodis, Dale E. Hoffman, Charles A. Puntar, Kurt P. Szabo
  • Patent number: 5097144
    Abstract: A driver circuit is disclosed for use in testing bi-directional transceiver semiconductor products using a minimum of time and number of product accessing pins. The driver includes a pair of controllable amplitude current sources whose output currents are selectably switched into or partially away from the commonly connected emitters of a current switch. The current switch is energized by a variable voltage source and produces the output test voltage.
    Type: Grant
    Filed: April 30, 1990
    Date of Patent: March 17, 1992
    Assignee: International Business Machines Corporation
    Inventors: Albert Y. Chang, Algirdas J. Gruodis, Dale E. Hoffman, Daniel E. Skooglund
  • Patent number: 5013944
    Abstract: A method of operating a delay circuit to impose a selected delay on an electronic signal the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method comprising the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.
    Type: Grant
    Filed: April 20, 1989
    Date of Patent: May 7, 1991
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey H. Fischer, Lawrence J. Grasso, Dale E. Hoffman, Daniel E. Skooglund, Diane K. Young
  • Patent number: 4924484
    Abstract: A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.
    Type: Grant
    Filed: October 27, 1988
    Date of Patent: May 8, 1990
    Assignee: International Business Machines Corp.
    Inventors: Lawrence J. Grasso, Dale E. Hoffman, Carroll E. Morgan, Charles A. Puntar, Diane K. Young
  • Patent number: 4779270
    Abstract: Disclosed is a method and circuit for reducing and maintaining constant overshoot in a high speed driver. The circuit includes a predriver circuit which is driven single endedly and a driver circuit which is differentially driven by the predriver outputs. The predriver and the driver are differential pairs, with commonly controlled individual transistor current sources. A diode has been added in series with each emitter of the differential pairs. Schottky diodes are preferable because of their low capacitance. The diodes increase the input switching voltage (the smallest input voltage swing that will cause the outputs to fully switch) of the differential pair because they must also be switched on and off. The increase results in an increase in effective transition time, which results in smaller overshoots because the circuit is being switched slower. The output amplitude of the driver is set by a voltage which controls the current source currents of the commonly controlled current sources.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: October 18, 1988
    Assignee: International Business Machines Corporation
    Inventors: Algirdas J. Gruodis, Dale E. Hoffman, Charles A. Puntar, Daniel E. Skooglund