Patents by Inventor Dale E. Pontius
Dale E. Pontius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971996Abstract: A charge pump circuit includes a charge pump configured to increase a voltage of an input signal to generate a voltage-boosted input signal, output the voltage-boosted input signal in response to a determination that the voltage-boosted input signal is greater than or equal to a threshold, and connect the charge pump to a supply voltage to pre-charge the charge pump in response to a determination that the voltage-boosted input signal is less than the threshold. The charge pump circuit includes bandgap reference generator configured to receive the voltage-boosted input signal and output, based on the voltage-boosted input signal, a voltage reference signal to a device that operates in accordance with the supply voltage.Type: GrantFiled: June 1, 2020Date of Patent: April 6, 2021Assignee: Marvell Asia Pte., Ltd.Inventors: Eric D. Hunt-Schroeder, John A. Fifield, Dale E. Pontius
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Publication number: 20200295653Abstract: A charge pump circuit includes a charge pump configured to increase a voltage of an input signal to generate a voltage-boosted input signal, output the voltage-boosted input signal in response to a determination that the voltage-boosted input signal is greater than or equal to a threshold, and connect the charge pump to a supply voltage to pre-charge the charge pump in response to a determination that the voltage-boosted input signal is less than the threshold. The charge pump circuit includes bandgap reference generator configured to receive the voltage-boosted input signal and output, based on the voltage-boosted input signal, a voltage reference signal to a device that operates in accordance with the supply voltage.Type: ApplicationFiled: June 1, 2020Publication date: September 17, 2020Inventors: Eric D. HUNT-SCHROEDER, John A. Fifield, Dale E. Pontius
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Patent number: 10699771Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.Type: GrantFiled: July 10, 2019Date of Patent: June 30, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. Fifield, Dale E. Pontius
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Patent number: 10673321Abstract: Methods produce IC devices that include a multiplexor that is electrically connected to a bandgap reference generator and a charge pump. The multiplexor receives voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator. The multiplexor outputs, to the charge pump, either: a retry signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are below a voltage threshold) or a pump signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are not below the voltage threshold). The pump signal causes the charge pump to output the voltage-boosted clock signal to the bandgap reference generator. The retry signal causes the charge pump to not output the voltage-boosted clock signal to the bandgap reference generator, and instead to precharge the charge pump.Type: GrantFiled: November 27, 2017Date of Patent: June 2, 2020Assignee: Marvell Asia Pte., Ltd.Inventors: Eric Hunt-Schroeder, John A. Fifield, Dale E. Pontius
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Publication number: 20190333568Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.Type: ApplicationFiled: July 10, 2019Publication date: October 31, 2019Inventors: John A. Fifield, Dale E. Pontius
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Patent number: 10438652Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.Type: GrantFiled: August 8, 2018Date of Patent: October 8, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. Fifield, Dale E. Pontius
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Publication number: 20190165669Abstract: Methods produce IC devices that include a multiplexor that is electrically connected to a bandgap reference generator and a charge pump. The multiplexor receives voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator. The multiplexor outputs, to the charge pump, either: a retry signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are below a voltage threshold) or a pump signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are not below the voltage threshold). The pump signal causes the charge pump to output the voltage-boosted clock signal to the bandgap reference generator. The retry signal causes the charge pump to not output the voltage-boosted clock signal to the bandgap reference generator, and instead to precharge the charge pump.Type: ApplicationFiled: November 27, 2017Publication date: May 30, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Eric Hunt-Schroeder, John A. Fifield, Dale E. Pontius
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Publication number: 20180350424Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.Type: ApplicationFiled: August 8, 2018Publication date: December 6, 2018Inventors: John A. FIFIELD, Dale E. PONTIUS
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Patent number: 10127970Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.Type: GrantFiled: March 21, 2017Date of Patent: November 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. Fifield, Dale E. Pontius
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Patent number: 9996648Abstract: The present disclosure relates to customization of a circuit layout using information from a netlist, and more particularly, to customization of a circuit layout using embedded formulas and a netlist. The system includes a CPU, a computer readable memory, and a computer readable storage device. The system also includes first program instructions to generate a graphical layout of a circuit, second program instructions to place a text formula on the graphical layout of the circuit, and third program instructions to activate the text formula in order to customize the graphical layout of the circuit. The first program instructions, the second program instructions, and the third program instructions of the system are stored on the computer readable storage device for execution by the CPU via the computer readable memory.Type: GrantFiled: April 29, 2016Date of Patent: June 12, 2018Assignee: GLOBALFOUNDRIES INC.Inventor: Dale E. Pontius
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Publication number: 20170316136Abstract: The present disclosure relates to customization of a circuit layout using information from a netlist, and more particularly, to customization of a circuit layout using embedded formulas and a netlist. The system includes a CPU, a computer readable memory, and a computer readable storage device. The system also includes first program instructions to generate a graphical layout of a circuit, second program instructions to place a text formula on the graphical layout of the circuit, and third program instructions to activate the text formula in order to customize the graphical layout of the circuit. The first program instructions, the second program instructions, and the third program instructions of the system are stored on the computer readable storage device for execution by the CPU via the computer readable memory.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventor: Dale E. Pontius
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Publication number: 20170194044Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.Type: ApplicationFiled: March 21, 2017Publication date: July 6, 2017Inventors: John A. FIFIELD, Dale E. PONTIUS
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Patent number: 9634557Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.Type: GrantFiled: July 10, 2014Date of Patent: April 25, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. Fifield, Dale E. Pontius
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Publication number: 20160013718Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.Type: ApplicationFiled: July 10, 2014Publication date: January 14, 2016Inventors: John A. FIFIELD, Dale E. PONTIUS
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Patent number: 8300489Abstract: Charge pump circuit includes a plurality of boost capacitors. An output charge of the charge pump circuit is adjusted by selecting a number of the boost capacitors at least one of using a digital control word and programming of a wiring level. A method of boosting supply voltage uses a charge pump circuit. The method includes adjusting an output charge of the charge pump circuit by selecting a number of boost capacitors at least one of using a digital control word and by programming of a wiring level.Type: GrantFiled: January 12, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: John A. Fifield, Thomas M. Maffitt, Dale E. Pontius
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Publication number: 20110170368Abstract: Charge pump circuit includes a plurality of boost capacitors. An output charge of the charge pump circuit is adjusted by selecting a number of the boost capacitors at least one of using a digital control word and programming of a wiring level. A method of boosting supply voltage uses a charge pump circuit.Type: ApplicationFiled: January 12, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. FIFIELD, Thomas M. MAFFITT, Dale E. PONTIUS
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Patent number: 6882583Abstract: A method and structure is disclosed for serially storing and retrieving fuse information to and from a non-scannable static random access memory (SRAM) array within an embedded DRAM structure. The SRAM array is part of a scan chain and is connected to upstream and downstream latches that make up the scan chain. Various data is serially scanned into the scan chain. As the data flows through the entire scan chain, the invention counts the number of bits scanned into the embedded DRAM structure using a counter. The counter can be included within the embedded DRAM structure. After the counter counts to an amount equal to the number of bits of storage of all downstream scan latches in the scan chain, the invention loads the fuse information into a shift register. When the shift register is full, the invention loads the contents of the shift register to a SRAM line. The lengths of the shift register and the SRAM line are equal to a fuse word.Type: GrantFiled: April 30, 2003Date of Patent: April 19, 2005Assignee: International Business Machines CorporationInventors: Kevin W. Gorman, Dale E. Pontius
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Publication number: 20040218454Abstract: A method and structure is disclosed for serially storing and retrieving fuse information to and from a non-scannable static random access memory (SRAM) array within an embedded DRAM structure. The SRAM array is part of a scan chain and is connected to upstream and downstream latches that make up the scan chain. Various data is serially scanned into the scan chain. As the data flows through the entire scan chain, the invention counts the number of bits scanned into the embedded DRAM structure using a counter. The counter can be included within the embedded DRAM structure. After the counter counts to an amount equal to the number of bits of storage of all downstream scan latches in the scan chain, the invention loads the fuse information into a shift register. When the shift register is full, the invention loads the contents of the shift register to a SRAM line. The lengths of the shift register and the SRAM line are equal to a fuse word.Type: ApplicationFiled: April 30, 2003Publication date: November 4, 2004Applicant: International Business Machines CorporationInventors: Kevin W. Gorman, Dale E. Pontius
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Patent number: 6674673Abstract: A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell.Type: GrantFiled: August 26, 2002Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Gregory Fredeman, Chorng-Lii Hwang, Toshiaki Kirihata, Dale E. Pontius
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Patent number: 6674676Abstract: A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell.Type: GrantFiled: May 23, 2003Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Gregory Fredeman, Chorng-Lii Hwang, Toshiaki Kirihata, Dale E. Pontius