Patents by Inventor Dale Edward Meehl

Dale Edward Meehl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9817068
    Abstract: Systems and methods efficiently bring additional variables into a Pseudo-Random Pattern Generator (“PRPG”) in the early cycles of an automatic test pattern generation (“ATPG”) process without utilizing any additional hardware or control pins. Overscanning (e.g., scanning longer than the length of the longest channel) for some additional cycles brings in enough variables into the PRPG. Data corresponding to earlier cycles of the ATPG process is removed.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 14, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vivek Chickermane, Krishna Vijaya Chakravadhanula, Brian Edward Foutz, Steev Wilcox, Paul Alexander Cunningham, David George Scott, Louis Christopher Milano, Dale Edward Meehl
  • Patent number: 9702934
    Abstract: Systems and methods disclosed herein provide for efficiently loading mask data to the mask register bits from the decompression network outputs of an ATPG system. The systems and methods also provide an elastic interface utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the number of input variables utilized during the loading of the mask data to the mask register bits.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: July 11, 2017
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Dale Edward Meehl, Vivek Chickermane
  • Patent number: 9470754
    Abstract: Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide care bits in early scan cycles of the ATPG process for sequential decompressors starting from a fixed state.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: October 18, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vivek Chickermane, Krishna Vijaya Chakravadhanula, Brian Edward Foutz, Steev Wilcox, Paul Alexander Cunningham, David George Scott, Louis Christopher Milano, Dale Edward Meehl
  • Patent number: 9448282
    Abstract: A system and method are provided for selective bit-wise masking of X-values in scan channels in an integrated circuit (IC) during a built-in self test (BIST). The composite mask pattern is selectively generated according to locations of X-values identified in a simulation of the IC. The composite mask pattern is stored on the IC and cyclically maintained while being applied to the operational scan results of the IC. The composite mask pattern is recycled over a plurality of scan iterations to effectively prevent the X-values from influencing the resulting signature of the BIST that represents a functional fingerprint of the IC and minimize storage requirements for the composite mask pattern.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: September 20, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventor: Dale Edward Meehl