Abstract: A Random Access Memory including a redundancy scheme wherein redundant memory elements are organized in a mixture of redundancy patches of various sizes, i.e., various number of word/ bit lines in each patch. The number of lines, e.g., 1, 2, 4 or 8 word or bit lines, in each of the patches is selected as appropriate with many different sized patches existing within the same redundancy reservoir. The size the particular patch selected depends on the size of the replaced defect detected during programming.

Abstract: A memory card design which allows for stackable memory cards so that a computer system's memory capabilities can be expanded by connecting a first memory card to sockets of the computer system's motherboard and then stacking subsequent memory cards on top of this first memory card. The memory card design includes connector sockets on a top surface of the card which allow for another card to be plugged into these sockets. Also, a presence detect serial EPROM and steer and encode logic are provided to assign a unique system address to each presence detect. The serial presence detect address select wiring are offset within the stack as are RAS lines so that all lines do not have to be hard-wired through each card of a stack of the present invention.

Abstract: An architecture and method of implementing an invalid data handling least recently used replacement mechanism in a cache memory system is provided that includes a first register stack, a second register stack and stack control logic. The first register stack includes registers for holding entry address information. The stack control logic includes logic for inhibiting the placement of invalidated entry addresses into a Most Recently Used register in the first register stack and directs that such invalidated entry addresses be input into the second register. The stack control logic further directs that any new entry addresses be placed in the first register stack where invalidated entry addresses has resided. A counter keeps count of the number of invalidated entry addresses input into the second register stack and toggles a multiplexer at a Least Recently Used Entry output of the first register stack to select as its output, the output of the second register stack.

Abstract: An address decode circuit for receiving address input signals, includes a device for detecting a change in the address input signals, and a device for generating a control signal in response to a detected change in the address input signals. A gating mechanism gates at least one address bit in the address input signals input to the address decode circuit with the control signal.