Abstract: A laser gyro built in test apparatus. A laser gyro includes a microprocessor which provides a high speed method of communicating test data to an external inertial navigation system. The microprocessor performs tests on the gyro including temperature sensor tests, dither drive tests, active current control tests, and reports on the expected life of the gyro. The gyro can be commanded from the external system to perform any number of the built in test functions. The built in test functions are periodically executed to evaluate the health of the laser gyro and are thereby incorporated in the monitor control loop of the laser gyro.

Abstract: The invention provides a laser gyro with a single transformer power supply. The power supply receives a single 15 volt DC supply that is converted to a 320 volt DC supply, a 280 volt DC supply and a 500 volt DC supply. The invention implements a Royer Oscillator by providing a transformer with four windings each center-tapped. Two control transistors control the output of the transformer. The invention also provides a high speed output controlled start-up to prevent meta-stability in the Royer Oscillator.

Abstract: A laser gyro start up apparatus and method that safely and quickly starts a laser gyro. A microprocessor sequences the mechanical and electrical systems of the laser gyro such that the gyro is started up quickly in the proper sequence. The microprocessor also executes tests on the gyro and provides a health signal in the timing sequence. The start up apparatus starts the laser block dither, laser discharge and acquires the path length controllers. Optical start up operations may be performed including the calibration of volts per mode.

Abstract: A high voltage start circuit includes a high voltage start module and high voltage pulse generator apparatus. The high voltage pulse generator amplifies a five volt pulse at 60 KHz duty cycle to an output of 280 volts pulses at approximately 50% duty cycle. A PN junction high voltage diode with a high forward voltage drop and a resistor divider drives and holds a first transistor out of saturation. A low voltage diode creates a dead band such that two high voltage start module transistors are never on at the same time. The high voltage module contains two high voltage blocking diodes which protect the laser gyro active current control circuitry during start up. Two small ballast resistors and a parallel 10 times voltage multiplier generate at least a 2500 VDC output. The high voltage start circuit is contained within a laser gyro housing and is configured to have a volume less than the volume of the ring laser gyro block.

Abstract: A dither stripper for laser gyro dither including a digital microcomputer which controls the stripping of the dither signal from the inertial navigation signal of the laser gyro. The dither stripper schedules internal A/D conversions using an A/D conversion arbitration scheme as well as calculates the expected system sample clock. Accurate dither stripping is achieved using a phase locked loop feedback system which compensates for real time changes in dither pickoff components while incorporating an accurate gain control mechanism.

Abstract: A direct digital dither drive for a laser gyro dither motor including a digital microcomputer which controls the dithering of a laser gyro to prevent lock in of the laser beams. The digital drive senses a dither position and schedules internal A/D conversions using an A/D conversion arbitration scheme. The period frequency and location of the minimum and maximum drive are determined using the microcontroller. Accurate dither drive is accomplished using a digital analog feedback system which compensates for real time changes in dither pickoff and dither drive components.

Abstract: A precision voltage reference incorporating at least one superlattice resonant tunneling diode and support electronics. The precision voltage reference is stable as to temperature and radiation.

Abstract: An alpha particle resistant memory cell and array with complementary, differential data in, data out and write enable inputs capable of independent, simultaneous read/write operations. During write operations, clocked differential write and data inputs steer cell current to induce differential cell voltages indicative of the stored data. During read operations, a read select input shifts the voltage levels of the selected cell to produce a distinguishable output which dominates over the other cells to appropriately steer current at a sense amplifier to identify the binary cell contents. A 64 row by 12 bit register stack, with split word write, master reset and read enable is also disclosed.

Abstract: An economical circuit of n transistors and m resistors (n=4, m=1 for Emitter Coupled Logic (ECL); n=3, m=0 for Current Mode Logic (CML)) interconnects to a fast differential feedback latch of r transistors and s resistors (r=12, s=9 for ECl; r=7, s=3 for CML) using two levels of series gating and one current source in order to establish scan/set testability of such latch. An additional interconnected circuit of v transistors and w resistors (b=2, w-1 for ECL; v=1, w=0 for CML) further establishes either a reset or a set capability for such latch. The economical total scan/set testable latch of x transistors and y resistors (x=18, y=11 for ECL; x=11, y=3 for CML) exhibits an excellent delay-power product since a single current is selectively steered into one of four different paths, the remaining three of which paths are shut down. Use of but a single current source provides further economy of silicon implementation.

Abstract: A circuit of 24 transistors and 16 resistors forming an interconnected constant current source, two differential current switches, and level shifter receives scan/set test data, clock, and enablement signals for, when connected to each of the set Q and clear Q output signals of a differential feedback latch, enabling scan/set testability of such latch. Both the latch and the connected circuit, forming in aggregate a scan/set testable latch, are implementable in Emitter Coupled Logic or current Mode Logic from standard cells of gate array technology using two levels of series gating and two current sources, which standard cells are otherwise useful for the generation of other logic macros. The differential feedback latch, experiencing but a small added capacitance from the connected circuit, continues to operate fast during normal operation, but is slow in operation for scan/set test wherein the connected circuit needs overcome differential feedback loops within the latch which are still active.

Abstract: Apparatus for controllably admitting a sample volume of engine exhaust into a bifurcated, closed-loop opacity chamber and wherein the exhaust sample is controllably directed away from the internal optics via symmetric flow inducing air guides. A pulsed light source is controllably directed through the opacity chamber and exhaust sample and the detected light is compared to a reference level so as to determine a relative measure of the sample's opacity. Attendant control circuitry permits the selected display of corresponding sample opacity and density values.