Abstract: A baseline restore circuit includes a current input for receiving a current pulse having a DC current baseline; a charge amplifier having an input coupled to the current input, and an output referenced to a DC voltage baseline; a feedback baseline restore circuit comprised of a switched capacitor integration circuit having an input coupled to the output of the charge amplifier, and an output coupled to the current input; and a sample control circuit controlling the switched capacitor circuit input to the integrator so that only the reference voltage baseline is sampled. The inputs to the sample control circuit are a window comparator, and a high rate pulse detector, both with inputs from the charge amplifier output.

Abstract: A baseline restore circuit includes a current input for receiving a current pulse having a DC current baseline; a charge amplifier having an input coupled to the current input, and an output referenced to a DC voltage baseline; a feedback baseline restore circuit comprised of a switched capacitor integration circuit having an input coupled to the output of the charge amplifier, and an output coupled to the current input; and a sample control circuit controlling the switched capacitor circuit input to the integrator so that only the reference voltage baseline is sampled. The inputs to the sample control circuit are a window comparator, and a high rate pulse detector, both with inputs from the charge amplifier output.

Abstract: An integrated application specific integrated circuit having a detection layer, a time delayed integration capability, data acquisition electronics, and a readout function is provided for detecting breast cancer in women. The detection layer receives x-ray radiation and converts the received energy to electron pairs, one of which is received by pixels. The time delay integration is on the chip and a part of the readout architecture. The detector may be a hybrid silicon detector (SiPD), a CdZnTe detector, or a GaAs detector.

Abstract: Signal charges in two charge coupled device (CCD) registers are subtracted one from the other by alternately passing them under a common, periodically clamped, normally floating sensing electrode. During those periods when the electrode is clamped, charge is shifted from the subtrahend register to the substrate region underlying the sensing electrode and charge, which has been shifted there previously from the minuend register, is shifted out of that region. During the intervening time periods, when the sensing electrode floats, the process is reversed, with charge from the minuend register being shifted under the sensing electrode and charge previously shifted there from the subtrahend register being shifted out. The resulting voltage reached by the sensing electrode during its floating intervals represents the difference between the charges in the two registers.

Abstract: A multi-channel multiplexer for converting multi-channel parallel information to single channel serial information. In the preferred embodiment, the invention utilizes the delay characteristics of charged-coupled devices (CCD) to sequentially delay simultaneous inputs and add them at the output thereby performing a parallel-to-serial multiplexing function. Multiple delay gate electrodes coupled to clocks having varying frequencies are utilized to sequentially delay the charge being transferred.

Abstract: A device for performing Haddamard transform operations including a first matrix of interconnected electronic cells, and a second matrix of interconnected electronic cells connected to the output of the first matrix, the electronic cells being charge coupled devices. A rectangular wave generator is electronically connected to the first and second matrices. The first matrix comprises a plural number of rows of such electronic cells serially connected to each other, the output of each one of the rows being connected to an input of each one of the cells corresponding to one of the rows of the second matrix. As a result a solution of on-focal plane Haddamard transform is obtained by recording the Haddamard sequencies at a common terminal of the second or output matrix.