Abstract: A signal generator circuit includes an oscillator operative to generate a first signal having a first frequency associated therewith, and a phase stepper circuit coupled to the oscillator. The phase stepper circuit is configured to receive a plurality of control signals indicative of respective phases of the first signal, and to generate a second signal as a function of the plurality of control signals. The second signal has a second frequency associated therewith that is a fractional multiple or a fractional division of the first frequency. The second signal has a phase associated therewith which changes with periods of the second signal.

Abstract: A signal generator circuit having enhanced control resolution includes a variable frequency oscillator having a first control input adapted to receive a first signal and at least a second control input adapted to receive a second signal. The second signal is afforded a weight which is substantially equal to a weight of a least significant bit of the first signal. The variable frequency oscillator is operative to generate an output signal having a frequency which varies as a function of the first and second signals. The signal generator circuit further includes a first counter, a first divider and a modulation circuit. The first counter is configurable for generating an output count based at least in part on a difference between a third signal presented to the signal generator circuit and a fourth signal indicative of the output signal, the output count including the first signal.

Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

Abstract: This disclosure relates to a cell-placeable variable-frequency digitally controlled oscillator (DCO) that consumes approximately the same current in a fast process corner as in the case of a slow process corner. By modulating the effective channel length of transistors in inverters, a fast process DCO may be slowed down to a desired frequency at nearly the same current consumption as that of a slow process DCO.

Abstract: A phase-locked loop includes a variable frequency generator, a comparator and a counter. The variable frequency generator is configurable for generating an output signal having a frequency which varies based at least in part on at least first and second control signals presented thereto. The comparator is configurable for receiving a first signal and a second signal, the first signal being an input signal presented to the phase-locked loop and the second signal being representative of the output signal from the variable frequency generator. The comparator generates a difference signal representative of a difference between a phase and/or a frequency of the first and second signals, the difference signal comprising the first control signal. The counter is configurable for generating an output count based at least in part on the difference signal from the comparator. The output count is a digital representation of the difference signal, the output count comprising the second control signal.

Abstract: A signal generator circuit includes an oscillator operative to generate a first signal having a first frequency associated therewith, and a phase stepper circuit coupled to the oscillator. The phase stepper circuit is configured to receive a plurality of control signals indicative of respective phases of the first signal, and to generate a second signal as a function of the plurality of control signals. The second signal has a second frequency associated therewith that is a fractional multiple or a fractional division of the first frequency. The second signal has a phase associated therewith which changes with periods of the second signal.

Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

Abstract: A telephone line-powered power supply, a method of operating the same and telephone line-powered ancillary equipment. In one embodiment, the power supply includes: (1) a transformer having a primary winding and a secondary winding and (2) an energy storage device (which may, but is not required to, be a capacitor) series-coupled to the primary winding, the primary winding and the energy storage device adapted to be coupled to, and provide a terminating resistance for, a telephone line. A node between the primary winding and the energy storage device provides DC power. Another embodiment employs a control switch to regulate an energy storage device, thereby dispensing with a need for the transformer.

Abstract: Sampling noise in an analog signal output from a codec, such as a speech codec, is reduced using linear interpolation. The output of a codec is input into two sample and hold circuits. The circuits generate two output signals (i.e. voltages) for each input signal. One of the output signals represents an interpolated signal located midway between an historical output signal and input signal. The generation of interpolated output signals reduces sampling noise.

Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

Abstract: A phase-locked loop (PLL) circuit having a voltage-controlled oscillator (VCO) is automatically calibrated for VCO center frequency and VCO gain during power up or responsive to a calibration signal. The VCO has several input voltage versus output frequency operating curves. During a calibration phase, proper VCO center frequency is selected by selecting one of the operating curves. VCO gain is then determined using the selected VCO operating curve. If the value of VCO gain is not within predetermined limits, VCO gain is adjusted accordingly, and the process of selecting a VCO operating curve and determining VCO gain is repeated.

Abstract: A phase-lock loop (PLL) circuit provides fast locking and low spurious modulation jitter through “gearshifting” control. The gearshifting PLL combines the advantages of low jitter from integer-N PLL and fast locking from fractional-N PLL. The PLL circuit includes a phase/frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). Control of the PLL circuit includes configuring the PLL circuit in two configurations, one for each phase of operation. The bandwidth of the loop filter is increased during the first phase of operation and the circuit is locked to a frequency that is close to the desired output frequency. During the second phase, the bandwidth of the loop filter is decreased and the circuit is locked to the desired frequency. The first configuration provides a relatively fast lock time compared to the lock time provided by the second configuration. The second configuration provides more stability than the first configuration.

Abstract: A phase-lock loop (PLL) circuit provides fast locking and low spurious modulation jitter through “gearshifting” control. The gearshifting PLL combines the advantages of low jitter from integer-N PLL and fast locking from fractional-N PLL. The PLL circuit includes a phase/frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). Control of the PLL circuit includes configuring the PLL circuit in two configurations, one for each phase of operation. The bandwidth of the loop filter is increased during the first phase of operation and the circuit is locked to a frequency that is close to the desired output frequency. During the second phase, the bandwidth of the loop filter is decreased and the circuit is locked to the desired frequency. The first configuration provides a relatively fast lock time compared to the lock time provided by the second configuration. The second configuration provides more stability than the first configuration.

Abstract: A phase-locked loop (PLL) circuit having a voltage-controlled oscillator (VCO) is automatically calibrated for VCO center frequency and VCO gain during power up or responsive to a calibration signal. The VCO has several input voltage versus output frequency operating curves. During a calibration phase, proper VCO center frequency is selected by selecting one of the operating curves. VCO gain is then determined using the selected VCO operating curve. If the value of VCO gain is not within predetermined limits, VCO gain is adjusted accordingly, and the process of selecting a VCO operating curve and determining VCO gain is repeated.

Abstract: A multifunction reset circuit including low power bandgap, a comparator, and an open drain buffer circuit--with the inclusion of four external components (three resistors and one capacitor) to provide undervoltage monitoring, power failure indicating, manual resetting and other reset control conditions to a single integrated circuit terminal, together with hysteresis tolerance.

Abstract: For use with a first transceiver, a system for, and method of, calibrating a first image reject mixer in the first transceiver and having first and second image products. In one embodiment, the system includes: (1) a second image reject mixer, associated with a second transceiver and tuned to a rejected one of the first and second image products. The system further includes a signal strength circuit, coupled to the second image reject mixer, that determines a signal strength of the rejected one. The system still further includes a trimmer, associated with the first image reject mixer, that trims the first image reject mixer to move the rejected one toward an optimal value of the signal strength.

Abstract: An integrated circuit formed within a substrate has a first circuit section and an active noise cancellation section located at least between the first circuit section and a noise source. The active noise cancellation section is coupled to the substrate and injects counter-charge into the substrate to isolate the first circuit section from noise produced by the noise source.

Abstract: A voltage-to-current converter comprises a first MOS transistor for receiving a voltage signal at a first gate and transferring a current signal between a first drain and a first source, a second MOS transistor for receiving a biasing voltage at a second gate and transferring the current signal between a second drain and a second source, and a biasing circuit for applying the biasing voltage of V.sub.C +V.sub.T +kV.sub.DS to the second gate such that the second transistor provides a substantially constant drain-to-source resistance of 1/.beta.V.sub.C, where V.sub.C is a constant voltage, V.sub.T is a threshold voltage for the second transistor, V.sub.DS is a drain-to-source voltage for the second transistor, k is a constant in the range of 1/3 to 2/3, and .beta. is a gain for the second transistor.

Abstract: An integrated circuit obtains improved ESD protection by way of a shunt protection circuit having a trigger level that exhibits a hysteresis effect with respect to voltage applied to the bondpads. The hysteresis is obtained by a string of voltage dropping transistors that produce a trigger voltage level at an intermediate node, and a shorting transistor that effectively removes at least one transistor from the string. In a typical case, a PNP bipolar transistor serves as the protective device in the circuit to carry the ESD current from the bondpads. An illustrative embodiment with p-channel voltage dropping transistors and an n-channel shorting transistor is shown, along with additional capacitive boost circuitry for speeding up circuit operation. In this manner, a high peak ESD current can be carried while ensuring non-conduction of the protection circuit for normal operating voltages, and also for voltages slightly in excess of normal power supply voltages.

Abstract: An integrated circuit is disclosed that includes a biquadratic filter in which the poles and zeroes are independently adjustable. The transfer function of the filter has a pair of zeroes in the numerator and a pair of complex conjugate poles in the denominator. The integrated circuit includes a first circuit for constructing the complex conjugate poles of the filter transfer function. The first circuit has an input port for receiving an input signal and an output port at which an output current representative of a filtered output signal is presented. The integrated circuit includes a second circuit for constructing, independently of the poles, the zeroes of the filter transfer function. The second circuit has an input port coupled to the input port of the first circuit for receiving the input signal. The second circuit includes a differentiator for differentiating the input signal to produce a differentiated input signal.