Abstract: Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is disclosed. Error correction coding according to a fixed-block size code, such as low density parity check (LDPC) coding, is implemented. A specific LDPC code with excellent error rate performance is disclosed.

Abstract: Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is disclosed. Error correction coding according to a fixed-block size code, such as low density parity check (LDPC) coding, is implemented. The codeword length, and codeword arrangement, are selected by determining a minimum number of OFDM symbol periods required for a payload size, and the number of available information bits in those symbol periods. A rule-based approach, for example in a table, is used to select the codeword length, and the number of codewords required. Shortening is then applied to the code, followed by determining whether puncturing or repeating of bits is necessary to efficiently use the available OFDM symbols.

Abstract: A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclosed. The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates.

Abstract: A communications transceiver for transmitting and receiving coded communications, with the coding corresponding to a low-density parity check code, is disclosed. A set of available code word lengths and code rates are to be supported by the transceiver. These available code word lengths and code rates are implemented as a subset of starting code word lengths, which are length-reduced by shortening and puncturing selected bit positions in the starting code word length to attain the desired one of the available code word lengths and code rates. The bit positions to be shortened and punctured are selected in a manner that avoids interference between the shortened and punctured bit positions, and that attains excellent code performance.

Abstract: Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.

Abstract: A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a probability value estimate and a check node value estimate, the probability value estimate and the check node value estimate associated with a parity check matrix. The system also comprises a plurality of parity check update modules (PCUMs) in parallel with each other, coupled to the first adder module and adapted to update the check node value estimate, and a second adder module coupled to the plurality of PCUMs and adapted to update the probability value estimate using the extrinsic estimate and the updated check node value estimate. The PCUMs process at least some columns of at least some rows of the parity check matrix in a serial fashion.

Abstract: A method of decoding in layers data received in a communication system, comprising receiving a codeword containing a plurality of elements and translating the plurality of elements into probability values by dividing the rows of at least one column of a parity check matrix associated with the codeword into groups and processing at least some of the groups separately.