Abstract: A superconducting oscillator/counter analog-to-digital converter (50) that provides simultaneous in-phase and quadrature-phase of an RF input signal. The RF input signal is converted to a series of SFQ input pulses by a superconducting voltage controlled oscillator (12). A clock circuit (26) generates a series of SFQ clock pulses. The SFQ input pulses and the SFQ clock pulses are applied to a pulse repulsion circuit (52) that outputs the SFQ input pulses and the SFQ clock pulses spaced apart in time. In one embodiment, the pulse repulsion circuit (52) includes two Josephson transmission lines (60, 62), where the magnetic coupling between the lines (60, 62) provides the SFQ pulse repulsion.

Abstract: The level of bias current (12) required by a superconductor integrated circuit (2 & 4) is lowered by separating the circuit into portions having separate ground planes and supplying the bias current to the circuit portion (2) in one ground plane in series (10) with that for the circuit portion (4) in another ground plane. To maintain DC isolation between those circuit portions, SFQ pulses inputted (SFQ IN) move across the separate ground planes through a pair of inductively coupled SQUIDS (3 & 5) that define a DC transformer; and a combiner (7) reconstitutes and outputs the SFQ pulses. To provide inductive coupling the DC transformer includes a primary (25) and isolated secondary (5) winding.

Abstract: An oscillator/multiply-accumulator AID converter (100) which simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter (100) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator (102). The voltage controlled oscillator (102) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit (104) that either passes or blocks the pulses depending on a gate control signal (103). When the pulses are passed by the gate circuit (104), a multiply-accumulator (106) multiplies the pulse by a binary coefficient (109) and accumulates the products (111) resulting from the multiplication during a predetermined time period.

Abstract: A control scheme for operating an oscillator/counter A/D converter so that it simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator. The voltage controlled oscillator receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit that, depending on a gate control signal, either blocks the pulses or passes the pulses to either an increment or a decrement port of a digital counter. When the pulses are passed by the gate circuit, the counter circuit accumulates the pulses during a sampling period.

Abstract: A control scheme for operating an oscillator/counter A/D converter (10) so that it simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter (10) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator (12). The voltage controlled oscillator (12) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit (14) that either passes or blocks the pulses depending on a gate control signal. When the pulses are passed by the gate circuit (14), a counter circuit (16) accumulates the pulses during a sampling period.

Abstract: A correlated superconductor single flux quantum oscillator-counter analog-to-digital (A/D) converter has a superconducting quantum interference device (SQUID) quantizer 20 with two Josephson junctions 24 and 26, each connected to a digital sampling and counting circuit with synchronized timing to increase the sampling rate or the bit resolution of the A/D converter. In a preferred embodiment, a plurality of SQUID quantizers 60 . . . 72 each with two Josephson junctions 74 . . . 88 are connected to a counter structure with precisely synchronized timing to further increase the sampling frequency and/or the bit resolution. A counter structure preferably comprises multiple rows 218, 240, 254 of single flux quantum flip-flops 220 . . . 234, 242 . . . 248, 256, 258 and parallel-serial converter/shift registers 236 250, 260 to produce an output digital data stream in serial form.

Abstract: An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto.

Abstract: An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto.