Patents by Inventor Dale J. Juenemann
Dale J. Juenemann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10956323Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.Type: GrantFiled: May 10, 2018Date of Patent: March 23, 2021Assignee: INTEL CORPORATIONInventors: Dale J. Juenemann, James A. Boyd, Robert J. Royer, Jr.
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Patent number: 10949356Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.Type: GrantFiled: June 14, 2019Date of Patent: March 16, 2021Assignee: Intel CorporationInventors: James A. Boyd, Robert J. Royer, Jr., Lily P. Looi, Gary C. Chow, Zvika Greenfield, Chia-Hung S. Kuo, Dale J. Juenemann
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Patent number: 10540505Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.Type: GrantFiled: September 29, 2017Date of Patent: January 21, 2020Assignee: Intel CorporationInventors: James A. Boyd, Dale J. Juenemann, Robert J. Royer, Jr.
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Publication number: 20190303300Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.Type: ApplicationFiled: June 14, 2019Publication date: October 3, 2019Inventors: James A. BOYD, Robert J. ROYER, JR., Lily P. LOOI, Gary C. CHOW, Zvika GREENFIELD, Chia-Hung S. KUO, Dale J. JUENEMANN
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Publication number: 20190251023Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.Type: ApplicationFiled: January 15, 2019Publication date: August 15, 2019Inventors: James A. BOYD, Dale J. JUENEMANN, Francis R. CORRADO
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Publication number: 20190102565Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: INTEL CORPORATIONInventors: JAMES A. BOYD, DALE J. JUENEMANN, ROBERT J. ROYER, JR.
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Patent number: 10204039Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.Type: GrantFiled: January 22, 2016Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: James A. Boyd, Dale J. Juenemann, Francis R. Corrado
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Publication number: 20190042415Abstract: A processor is described. The processor includes register space to accept input parameters of a software command to move a data item out of computer system storage and into persistent system memory. The input parameters include an identifier of a software process that desires access to the data item in the persistent system memory and a virtual address of the data item referred to by the software process.Type: ApplicationFiled: June 12, 2018Publication date: February 7, 2019Inventors: James A. BOYD, Dale J. JUENEMANN
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Publication number: 20190042414Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.Type: ApplicationFiled: May 10, 2018Publication date: February 7, 2019Inventors: Dale J. JUENEMANN, James A. BOYD, Robert J. ROYER, JR.
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Publication number: 20190026226Abstract: A disclosed example to manage intermittently connectable storage media includes a cache initializer to initialize a nonvolatile cache corresponding to an intermittently connectable storage media device connected to a host system; a cache flush manager to change a cache flush mode associated with the nonvolatile cache from a cache write through mode to a cache write back mode based on the intermittently connectable storage media device being disconnected from the host system; a cache access manager to maintain the nonvolatile cache after the intermittently connectable storage media device is disconnected, and in response to a data access request corresponding to the intermittently connectable storage media device, perform a corresponding data access operation using the nonvolatile cache.Type: ApplicationFiled: July 24, 2017Publication date: January 24, 2019Inventors: James A. Boyd, Dale J. Juenemann
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Patent number: 9870169Abstract: Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.Type: GrantFiled: September 4, 2015Date of Patent: January 16, 2018Assignee: Intel CorporationInventors: Anand S. Ramalingam, Dale J. Juenemann, Pranav Kalavade
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Publication number: 20170286311Abstract: In one embodiment, repetitive address indirection is employed to repetitively redirect write operations to different physical locations of the memory. In one embodiment, write data for every write operation is automatically, unconditionally and repetitively redirected to physical addresses in a memory in a circular sequence of physical addresses of the memory independently of, that is without regard to, the logical address of each write operation. As a result, successive write operations to the memory are automatically evenly distributed over the memory, even if repeatedly directed to the same or similar logical address. Other aspects are described herein.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Dale J. JUENEMANN, Anand S. RAMALINGAM
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Publication number: 20170075812Abstract: Technologies for managing a read cache of a solid state drive include establishing a read cache in an otherwise unused region of non-volatile memory of the solid state drive. To do so, a memory region of the non-volatile memory corresponding to the read cache is converted to single-level cell (SLC) mode. For example, the memory region may be converted from a multi-level cell (MLC) or a triple-level cell (TLC) mode to the SLC mode. A drive controller of the solid state drive manages data in the read cache based on a read count associated with the data. For example, data having a relatively high read count may be inserted into the read cache and data having a relatively lower read count may be evicted from the read cache over time. The size of the read cache may be dynamically adjusted over time based on available space and/or operating requirements.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Inventors: Ning Wu, Dale J. Juenemann, Neeraj Sharma, Ramkarthik Ganesan
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Publication number: 20170068482Abstract: Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.Type: ApplicationFiled: September 4, 2015Publication date: March 9, 2017Applicant: INTEL CORPORATIONInventors: ANAND S. RAMALINGAM, DALE J. JUENEMANN, PRANAV KALAVADE
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Publication number: 20160283385Abstract: A method is described that includes performing the following by a device driver of a non volatile storage device: caching information targeted for the storage device into a non volatile region of a system memory without writing the information through into the storage device.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Inventors: James A. Boyd, Sanjeev N. Trika, Dale J. Juenemann
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Publication number: 20160217069Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.Type: ApplicationFiled: January 22, 2016Publication date: July 28, 2016Inventors: James A. Boyd, Dale J. Juenemann, Francis R. Corrado
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Patent number: 9348405Abstract: Systems and techniques for control of storage device power states are described herein. In some embodiments, a control system for a storage device of a computing device may include receiver logic to receive a proximity signal indicative of a distance of a user from a proximity sensor, transition logic to determine that the proximity signal satisfies out-of-proximity criteria and generate an out-transition signal based at least in part on the determination that the proximity signal satisfies the out-of-proximity criteria, and state-change logic to cause a change in a power state of the storage device from a first power state to a second power state, in response to the out-transition signal, wherein the storage device consumes less power in the second power state than in the first power state. Other embodiments may be described and/or claimed.Type: GrantFiled: December 24, 2013Date of Patent: May 24, 2016Assignee: Intel CorporationInventors: Assar Badri, Dale J. Juenemann, Scott E. Burridge
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Patent number: 9244848Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.Type: GrantFiled: October 10, 2011Date of Patent: January 26, 2016Assignee: Intel CorporationInventors: James A. Boyd, Dale J. Juenemann, Francis R. Corrado
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Publication number: 20150177817Abstract: Systems and techniques for control of storage device power states are described herein. In some embodiments, a control system for a storage device of a computing device may include receiver logic to receive a proximity signal indicative of a distance of a user from a proximity sensor, transition logic to determine that the proximity signal satisfies out-of-proximity criteria and generate an out-transition signal based at least in part on the determination that the proximity signal satisfies the out-of-proximity criteria, and state-change logic to cause a change in a power state of the storage device from a first power state to a second power state, in response to the out-transition signal, wherein the storage device consumes less power in the second power state than in the first power state. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 24, 2013Publication date: June 25, 2015Inventors: Assar Badri, Dale J. Juenemann, Scott E. Burridge
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Publication number: 20130268731Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.Type: ApplicationFiled: October 10, 2011Publication date: October 10, 2013Inventors: James A. Boyd, Dale J. Juenemann, Francis R. Corrado