Patents by Inventor Dale J. Skelton
Dale J. Skelton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6744243Abstract: A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the integrated circuit. The step down power supply is operable to receive an input voltage and to generate an output voltage based on the input voltage. The feedback compensation circuit includes a line regulation circuit. The line regulation circuit is operable to receive the input voltage and a reference voltage. The line regulation circuit is also operable to generate an offset voltage based on the input voltage and the reference voltage.Type: GrantFiled: June 28, 2001Date of Patent: June 1, 2004Assignee: Texas Instruments IncorporatedInventors: David G. Daniels, Dale J. Skelton, Ayesha I. Mayhugh, David A. Grant
-
Publication number: 20030001551Abstract: A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the integrated circuit. The step down power supply is operable to receive an input voltage and to generate an output voltage based on the input voltage. The feedback compensation circuit includes a line regulation circuit. The line regulation circuit is operable to receive the input voltage and a reference voltage. The line regulation circuit is also operable to generate an offset voltage based on the input voltage and the reference voltage.Type: ApplicationFiled: June 28, 2001Publication date: January 2, 2003Applicant: Texas Instruments IncorporatedInventors: David G. Daniels, Dale J. Skelton, Ayesha I. Mayhugh, David A. Grant
-
Patent number: 6372586Abstract: A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain. Gate regions are formed between the alternating source and drain diffusions. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a source and a drain bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive copper layer.Type: GrantFiled: May 8, 2000Date of Patent: April 16, 2002Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Dave Cotton, Dale J. Skelton
-
Patent number: 6160388Abstract: A DC-DC converter that generates a sense signal representing a voltage drop across a low-side switch when the low-side switch is on. The sense signal is inverted and stored in a "hold" capacitor until the beginning of the next switching cycle. More specifically, an input node receives an input voltage V.sub.IN. A driver stage coupled to the input node and to a reference node chops V.sub.IN into a square wave under control of a PWM signal. The chopped V.sub.IN signal is coupled to an intermediate output node. An output stage coupled to the intermediate output node converts the chopped V.sub.IN signal to an output voltage V.sub.OUT to a load coupled to an output node. A sense unit coupled to sense a voltage on the intermediate output node generates a voltage signal indicating current flowing in the load.Type: GrantFiled: December 17, 1998Date of Patent: December 12, 2000Assignee: Texas Instruments IncorporatedInventors: Dale J. Skelton, Chao-Chih Chiu, Taylor R. Efland
-
Patent number: 6150722Abstract: A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain. Gate regions are formed between the alternating source and drain diffusions. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a source and a drain bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive copper layer.Type: GrantFiled: October 4, 1995Date of Patent: November 21, 2000Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Dave Cotton, Dale J. Skelton
-
Patent number: 6147526Abstract: A DC--DC converter having an input node receiving an input voltage V.sub.IN and generating an output voltage V.sub.OUT. A reference voltage generator provides a voltage V.sub.REF and a hysteresis voltage generator provides a voltage V.sub.HYST. A first comparator generates a signal determined from a difference between V.sub.REF and V.sub.OUT. A second comparator generates a signal determined from a difference between V.sub.OUT and V.sub.HYST. A latch is coupled to receive the outputs of the first and second comparators, and to generate an output. A driver circuit receives the latch output and generates a PWM signal used to switch the output stage. A double pulse suppression circuit masks off the latch inputs for a preselected time during the switching intervals fo the main power transistors to eliminate noise jitter.Type: GrantFiled: December 16, 1998Date of Patent: November 14, 2000Assignee: Texas Instruments IncorporatedInventors: Dale J. Skelton, Steven C. Jones, Taylor R. Efland, Lester L. Hodson
-
Patent number: 6140702Abstract: A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art.Type: GrantFiled: May 28, 1997Date of Patent: October 31, 2000Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Dale J. Skelton, Quang X. Mai, Charles E. Williams
-
Patent number: 6140150Abstract: A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art.Type: GrantFiled: April 14, 1999Date of Patent: October 31, 2000Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Dale J. Skelton, Quang X. Mai, Charles E. Williams
-
Patent number: 5859456Abstract: An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer.Type: GrantFiled: September 9, 1996Date of Patent: January 12, 1999Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, David Cotton, Dale J. Skelton
-
Patent number: 5744843Abstract: CMOS power device (10) is provided. A tank region (62) is formed in a semiconductor substrate (60). A polysilicon gate layer (34) is disposed above the tank region (62) and defines a plurality of source and drain diffusion openings (38 and 36) having rounded inner corners (40). A plurality of backgate contact regions (42) are segmented and are formed in vacancies in a plurality of source regions (30).Type: GrantFiled: August 28, 1996Date of Patent: April 28, 1998Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Dale J. Skelton
-
Patent number: 5728594Abstract: An interconnection structure and method for a multiple transistor integrated circuit power device is disclosed. A power integrated circuit is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form source and drain busses. Polysilicon gate busses are provided as well. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting on resistance for the transistors on the integrated circuit is substantially reduced by the use of the thick third metal layer.Type: GrantFiled: June 7, 1995Date of Patent: March 17, 1998Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, David Cotton, Dale J. Skelton
-
Patent number: 5710495Abstract: Apparatus and method (10, 40) for measuring an average motor current in a pulse width modulation driven motor are provided. A sensor (20) is coupled to the motor to measure a motor winding current. A first current source (26) generates a first current generally proportional to the motor winding current. A second current substantially proportional to a chopped output voltage is also produced and subtracted from the first current. A circuitry (28) receives the difference between the first and second currents and generates an output voltage indicative of the average motor current. The output voltage is chopped by a circuit (32, 34) that produces a waveform at substantially the same duty cycle and phase as the pulse width modulation waveform driving the motor.Type: GrantFiled: August 14, 1996Date of Patent: January 20, 1998Assignee: Texas Instruments IncorporatedInventor: Dale J. Skelton
-
Patent number: 5468984Abstract: An interconnection structure and method for a multiple zener diode ESD protectoin circuit for power semiconductor devices. A plurality of lateral Zener diodes is formed. Each device is formed of a plurality of cathode and anode diffusion regions to be coupled together to form the cathode and anode of one or more Zener diodes. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting Zener diodes are coupled together in an ESD structure using the second level busses and the thick copper third level busses.Type: GrantFiled: November 2, 1994Date of Patent: November 21, 1995Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Dave Cotton, Dale J. Skelton
-
Patent number: 5257175Abstract: A voltage regulation circuit for use in "H" bridge circuit applications utilizes feedback networks to provide analog voltage regulation of the output nodes during switching of inductive loads. The regulation of the ouptut nodes during switching of inductive loads eliminates substrate current injection.Type: GrantFiled: May 8, 1992Date of Patent: October 26, 1993Assignee: Texas Instruments IncorporatedInventors: Dale J. Skelton, Kuok Y. Ling, Myron G. Manternach