Abstract: A regulator includes an error amplifier with a first input coupled to receive a reference voltage and a second input coupled to receive a feedback signal. A driver transistor provides an output voltage of the regulator that powers a memory. A replica transistor provides a replica voltage that powers a replica of the memory. A first ratio of a size of the replica of the memory to a size of the memory is less than one, and a second ratio of a drive strength of the replica transistor to a drive strength of the driver transistor is less than one. Each of the first ratio and the second ratio is at most 1/500. Switching circuitry provides one of the output voltage or the replica voltage as the feedback signal to the error amplifier.

Abstract: A regulator includes an error amplifier with a first input coupled to receive a reference voltage and a second input coupled to receive a feedback signal. A driver transistor provides an output voltage of the regulator that powers a memory. A replica transistor provides a replica voltage that powers a replica of the memory. A first ratio of a size of the replica of the memory to a size of the memory is less than one, and a second ratio of a drive strength of the replica transistor to a drive strength of the driver transistor is less than one. Each of the first ratio and the second ratio is at most 1/500. Switching circuitry provides one of the output voltage or the replica voltage as the feedback signal to the error amplifier.

Abstract: An integrated circuit includes a power switch coupled between a first voltage supply node and an internal voltage supply node and a switch control circuit coupled to a control electrode of the power switch. The switch control circuit includes a driver circuit coupled between a second voltage supply node and a third voltage supply node, a pass-gate having a first node coupled to an output of the driver circuit and a second node coupled to the control electrode of the power switch, a pull-up transistor having a first current electrode coupled to the first voltage supply node, a second current electrode coupled to the control electrode of the power switch, and a bias circuit having a bias output configured to provide a higher voltage between the first and second power supply nodes as a bias voltage to a body electrode of the pull-up transistor.

Abstract: An integrated circuit includes a power switch coupled between a first voltage supply node and an internal voltage supply node and a switch control circuit coupled to a control electrode of the power switch. The switch control circuit includes a driver circuit coupled between a second voltage supply node and a third voltage supply node, a pass-gate having a first node coupled to an output of the driver circuit and a second node coupled to the control electrode of the power switch, a pull-up transistor having a first current electrode coupled to the first voltage supply node, a second current electrode coupled to the control electrode of the power switch, and a bias circuit having a bias output configured to provide a higher voltage between the first and second power supply nodes as a bias voltage to a body electrode of the pull-up transistor.

Abstract: A first voltage scaling power switch is coupled to a first power supply terminal for providing power to a first circuit portion, and a second voltage scaling power switch is coupled between the first power supply terminal providing power to a second circuit portion. A common power rail is coupled the first and second power input nodes during respective voltage scaling modes of the first and second circuit portions. A feedback circuit coupled to the common power rail provides a feedback signal to a control input of the first voltage scaling power switch to regulate a voltage provided by the first power switch, and to a control input of the second voltage scaling power switch to regulate a voltage provided by the second voltage scaling power switch.

Abstract: A method for forming al buried contact begins by forming an exposed contact area (22) of a substrate (10) having a surface (11). An undoped or lightly doped layer of polysilicon (32) is formed in contact with the contact area (22). A contiguous masking layer (36) is formed over one or more of the contact areas (22) to cover a contact portion of the layer (32) while exposing other portions of the layer (32). The other portions of the layer (32) are doped with dopant atoms (44). A heat cycle is used to laterally drive the dopant atoms (44) through the layer (32) and downward through a substrate surface (11) to form buried contact substrate-diffused regions (54). The resulting regions (54) have improved voltage punch-through resistance to laterally adjacent electrical diffusion regions since the masking layer (36) creates a longer thermal diffusion path for the dopant atoms which eventually reside in the regions (54).