Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine.

Abstract: Embodiments of the invention provide a method and apparatus for automatically evaluating and allocating resources in a cell based system. In one method embodiment, the present invention receives a request to generate a cell based system of resources. A list of allocatable resources having corresponding evaluation data is then accessed. The request for the cell based system is then compared with the list of allocatable resources having corresponding evaluation data. The allocatable resources are then assigned to the cell based system.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple functional units of a same type. The method includes opportunistically scheduling a redundant operation on one of the functional units that would otherwise be idle during a cycle.

Abstract: An example memory error ranking system is provided. The system may include an error detector logic that detects memory errors and a ranking logic that ranks the quality of a memory location based on memory errors detected by the error detector logic.

Abstract: Methodology, systems and media associated with selectively allocating memory are described. One exemplary method embodiment comprises receiving a quality data that identifies the quality of one or more allocatable subsets of a memory and selectively allocating a subset of memory from the allocatable memory to an application based, at least in part, on memory quality as identified in the quality data.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of program code and diagnostics code. The diagnostic code is scheduled to be executed on the selected execution unit. The program code is scheduled to be executed on remaining execution units of the same type.

Abstract: A printed circuit board comprises a conductive layer and a via transecting the conductive layer. The printed circuit board comprises a pattern of conductive material having a plurality of voids in the conductive layer near the via.

Abstract: An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations. The system may also include a memory quality assurance logic configured to logically replace a first memory location with a second memory location, to initiate testing logically isolated memory locations, and to selectively logically remove tested memory locations based on the testing. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the application. It is submitted with the understanding that it will not be employed to interpret or limit the scope or meaning of the claims 37 CFR 1.72(b).

Abstract: An example memory scrubbing logic is provided. The logic may be operably connectable to a main memory and a processor. The memory access logic may include a memory for mirroring a main memory location and a logic for scrubbing the main memory location.

Abstract: One embodiment disclosed relates to a method of providing CPU functional testing. Operations are executed on multiple functional units of a same type in the CPU. The outputs of the multiple functional units are automatically compared. The results of the comparison are checked only for redundant operations. Another embodiment disclosed relates to a microprocessor with built-in functional testing capability. The microprocessor includes multiple functional units of a same type and registers that receive outputs from the multiple functional units. In addition, comparator circuitry is built-in that also receives the outputs from the multiple functional units and compares the outputs to provide functional testing.

Abstract: One embodiment disclosed relates to a method of executing program code on a target microprocessor with multiple CPU cores thereon. One of the CPU cores is selected for testing, and inter-core context switching is performed. Parallel execution occurs of diagnostic code on the selected CPU core and the program code on remaining CPU cores. Another embodiment disclosed relates to a microprocessor having a plurality of CPU cores integrated on the microprocessor chip. Inter-core communications circuitry is coupled to each of the CPU cores and configured to perform context switching between the CPU cores.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor. A cycle is identified during which a functional unit would otherwise be idle. A diagnostic operation is opportunistically scheduled for execution on the functional unit during that cycle, and a comparison is scheduled to compare a result from executing the diagnostic operation with a corresponding predetermined result.

Abstract: One embodiment disclosed relates to a microprocessor for targeted fault-tolerant computing. The microprocessor's decode circuitry is configured to decode a fault-tolerant version of an instruction and a non-fault-tolerant version of the instruction distinctly from each other. The microprocessor's execution circuitry is configured to execute the fault-tolerant version of the instruction with redundancy checking and to execute the non-fault-tolerant version of the instruction without redundancy checking.

Abstract: A printed circuit board includes a first conductive plane and a second conductive plane substantially parallel to the first conductive plane. The printed circuit board includes a via signal barrel transecting the first and second conductive planes and a first anti-pad positioned between the first conductive plane and the via signal barrel. The first anti-pad has a first voided area. The printed circuit board includes a second anti-pad positioned between the second conductive plane and the via signal barrel. The second anti-pad has a second voided area. The first voided area does not completely overlap the second voided area.

Abstract: One embodiment disclosed relates to a printed circuit assembly (PCA) with built-in circuitry to detect and communicate an interconnect failure. The PCA includes a connector, a continuity detect circuit, and an interface circuit. The connector is configured to interconnect to an electronic unit. The continuity detect circuit is coupled to the connector for detection of continuity failure in the interconnect. The interface circuit is coupled to the continuity detect circuit for communicating data pertaining to status of the interconnect to system management.

Abstract: One embodiment disclosed relates to a printed circuit board (PCB) with built-in circuitry to test connector loading. The PCB includes at least the connector to be tested, an indicator circuit, and a switch. The connector is configured to interconnect to a card. The switch couples the connector to the indicator circuit, and integrity of the interconnection between the card and the connector is indicated by the indicator circuit.

Abstract: One embodiment disclosed relates to a printed circuit assembly (PCA) with built-in circuitry to detect and communicate an interconnect failure. The PCA includes a connector, a continuity detect circuit, and an interface circuit. The connector is configured to interconnect to an electronic unit. The continuity detect circuit is coupled to the connector for detection of continuity failure in the interconnect. The interface circuit is coupled to the continuity detect circuit for communicating data pertaining to status of the interconnect to system management.

Abstract: One embodiment disclosed relates to a printed circuit board (PCB) with built-in circuitry to test connector loading. The PCB includes at least the connector to be tested, an indicator circuit, and a switch. The connector is configured to interconnect to a card. The switch couples the connector to the indicator circuit, and integrity of the interconnection between the card and the connector is indicated by the indicator circuit.