Patents by Inventor Dale K. Seppa

Dale K. Seppa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5471482
    Abstract: A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: November 28, 1995
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, Donald W. Mackenthun, Philip J. Fye, Gerald J. Maciona, Jeff A. Engel, Ferris T. Price, deceased, Dale K. Seppa
  • Patent number: 5416362
    Abstract: An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: May 16, 1995
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, Fernando W. Arraut, Dale K. Seppa
  • Patent number: 4209846
    Abstract: A method of and an apparatus for distinguishing between transient and solid errors within a single-error-correcting semiconductor memory storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes and for notifying the associated data processing system of required maintenance action. The method utilizes an error logging store (ELS) that is comprised of a plurality of memory error registers one for each separately associated word group within the MSU. Each memory error register contains storage for: (1) the Error Correction Code (ECC) defined, failing bit position; (2) the single bit error counter; (3) the multiple single bit error tag; and (4) the multiple bit error tag. Upon detection of an error within a word group, the associated memory error register is accessed to determine the history of previously detected errors within that word group.
    Type: Grant
    Filed: December 2, 1977
    Date of Patent: June 24, 1980
    Assignee: Sperry Corporation
    Inventor: Dale K. Seppa