Abstract: An internal signal within a SONET element has a transport format having overhead and payload mapped in a manner similar to the Synchronous Optical Network standard mapping, except having selected overhead bytes defined differently, including a byte used for communicating odd parity calculated over an odd number of bytes of a frame of the transport format to determine correct or incorrect parity, selected bytes used for inter-module automatic protection switching, and a pointer having a selected fixed value, along with an adjusted virtual tributary pointer in a virtual tributary mode.

Abstract: Redundant facility payload signals (12, 14) received by redundant interface modules (16, 18) are redundantly provided (28, 30; 32, 34) to redundant downstream modules (24, 26) in an equipment (10). A non-symmetrical facility protection algorithm is resident in the B interface module (18). Symmetrical equipment protection algorithms are independently resident and operative in each module of pairs of identical A and B modules at each stage of the data stream. Module or data failures result in switchover only of the disabled data path or module so that the ability to transport payload is maintained and other modules or data paths are unaffected. Facility switchover is effected by detecting a working line failure and transmitting commands to switch the protection line to the A path modules. Equipment switchover is effected by checking for a working or protection module failure independently in each path and independently communicating independent switchover decisions to the other side and downstream.

Abstract: Existing infrastructures such as DS1 or E1 are used at currently accepted rates to carry a third more information by using a hybrid encoding technique wherein a 4B3T encoding is done for the payload bits, while a 1B1T encoding technique is used for framing information. In this way, for example, a DS1 can be used at 1.54 Mbit per second to carry 2.058 Mbits of binary payload, while respecting the 8 kilobits of framing expected by DS1 hardware. Similarly, for example, an E1 infrastructure can be used at the accepted 2.048 Mbit per second rate to carry 2.560 Mbits of binary payload plus 128 kilobits of binary framing/CRC without having to change the accepted E1 framing techniques.

Abstract: A virtual tributary (VT) or tributary unit (TU) of a selected size is multiplexed with transport overhead and further multiplexed with framing bandwidth of an underlying transport technology for providing a virtual tributary/tributary unit plus transport link overhead plus transport framing for transport on a selected transport technology. This enables individual virtual tributaries/tributary units to be transported with defined line overhead and using existing transport technology framing. Several examples of underlying transport technologies used in conjunction with selected transport formats for VT-1.5 and VT-2 superframes are shown.

Abstract: A SONET pointer interpretation in system which an Alarm Indication Signal (AIS) of a first type is interpreted as a subset of Loss of Pointer (LOP) of a first type. Specific events are defined for entering an AIS type 1 state and for exiting this state. Specific events are also defined for entering an LOP type 1 state and for exiting this state. Finally, a truth table is defined for mapping these states into a valid pointer (NORM) state, an AIS of a second type state and an LOP of a second type state.

Abstract: A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Abstract: In pulse code modulation communications systems where network links, using A, AB and ABCD signaling systems having different sized bit patterns and signaling rates for signaling operations, are interfaced, apparatus is provided to control the mapping of signaling patterns at signaling rate conversion boundaries.

Abstract: There is described a processing register particularly adapted for use in digital processing systems to implement various digital functions as high order digital filters and other structures which presently require complicated integrated circuit arrangements.The processing register operates in five modes which are a shift register mode with multiple fixed delays, a shift register with multiple fixed delays and a time slot interchanger, a shift register mode with an alternating word pair interchanger, a programmable delay shift register and as a discrete fourier transform preprocessing module.The processing register is particularly adaptable to operate with a high speed multiplier to implement various digital processing functions. In order to accommodate mode operation the processing register contains a main shift register and a computation register which are under the control of a control register which register accepts a control input word having bits thereof indicative of a particular mode of operation.